Apparatus for detecting a preamble in a bi-phase data recovery system

• US 4,054,950 A
• Filed: 04/29/1976
• Issued: 10/18/1977
• Est. Priority Date: 04/29/1976
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Boone, James G.
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/681,674
• Time in Patent Office: 537 Days
• Field of Search: 340/172.5, 307/208, 307/220 R, 307/231, 307/232, 307/269, 328/72, 328/108, 328/109, 328/110, 328/119, 328/120, 328/139, 328/179, 235/92 FQ, 235/92 TF, 235/92 PE, 364/900
• US Class Current: 375/316
• CPC Class Codes: G11B 20/12 Formatting, e.g. arrangement of data block or words on the record carriers within interface between computers and data recorders G06F3/06
• CPC Class Codes: G11B 27/3027 used signal is digitally coded
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

In order to detect the eminent reception of a valid bit serial message, a preamble constituting a string of predetermined number of clock pulses only is employed. Prior to detection of the preamble, each clock and data pulse from the raw data stream is applied to the increment input of a resettable counter. Each clock pulse is also used to trigger a monostable multivibrator which issues a pulse approximating three-fourths of a cell period. This pulse is ANDed with the next subsequent data period, and if a data "1" bit is detected, the satisfied condition is used to reset the counter. Thus, the counter can only reach a terminal count if a valid preamble is received. When the counter attains its terminal count, a latch flip-flop is set and a resultant "separation enable" signal issues to activate straightforward logic for separating the incoming clock and data pulses. Setting the latch also disables the preamble detection logic until an "end of data field" code is sensed whereupon the counter and latch are both reset to resume observation of the raw data stream for a preamble.

Claims

1. Apparatus for detecting an all clock pulse preamble to an encoded digital message having clock pulse and data pulse components, comprising:

A. a counter having an input adapted to receive said encoded digital message and to increment in response to pulses, a reset input, and an output for issuing an output signal when said counter reaches a predetermined count, said predetermined count corresponding to the number of clock pulses contained in the clock pulse preamble of said encoded digital message;

B. bistable latch means having a first input coupled to said counter output and responsive to an output signal therefrom to assume a first state indicating receipt of a clock pulse preamble, said bistable latch means having a second input responsive to a signal applied thereto for assuming a second state indicating non-receipt of a clock pulse preamble;

C. gate means operatively connected to said bistable latch means for providing an output pulse when said bistable latch means is in said second state and a pulse is received from said encoded digital message;

D. monostable means having an input and an output, said monostable means issuing an output pulse having a predetermined time duration in response to an input pulse applied thereto from said gate means, said predetermined time duration being less than the time period between successive clock pulses; and

E. reset means coupled to said counter and responsive to the simultaneous occurrence of an output pulse from said monostable means and a data pulse from said encoded digital message for resetting said counter prior to said counter reaching said predetermined count.

2. The apparatus of claim 1 in which said reset means is also coupled to said second input of said bistable latch means to place said bistable latch means in its second state when said counter is reset.

3. The apparatus of claim 2 which further includes:

A. separation means for controllably separating clock pulses and data pulses from the encoded digital message; and

B. means responsive to said first state of said bistable latch means for enabling said separation means.

4. The apparatus of claim 1 in which said reset means is an AND gate having an output and an OR gate having one input connected to the output of said AND gate, and another input operative for receiving a termination of encoded digital message signals, the output of said OR gate coupled to said counter.