Memory device and method of testing the same

• US 4,055,754 A
• Filed: 12/22/1975
• Issued: 10/25/1977
• Est. Priority Date: 12/22/1975
• Status: Expired due to Term

• Current Assignee: Gilman D. Chesley
• Original Assignee: Gilman D. Chesley
• Inventors: Chesley, Gilman D.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/642,765
• Time in Patent Office: 673 Days
• Field of Search: 235/153 AC, 235/153 AM, 324/73 R, 340/172.5, 340/174 ED, 445/1
• US Class Current: 714/720
• CPC Class Codes: G11C 11/4078 Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells protection of memory contents during checking or testing G11C29/52
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

Integrated circuit memory device and method of testing the same wherein test logic is included in the device for detecting the presence of predetermined patterns applied to the memory cells. The cells are tested in groups to reduce the amount of time required for the test.

Claims

1. In an integrated circuit memory device:

a plurality of memory cells, means for writing data into and reading data out of the memory cells, first coincidence gate means responsive to data read simultaneously out of a group of the memory cells for determining whether all of the group is of a first logic level, second coincidence gate means responsive to data read simultaneously out of the group of cells for determining whether all the data from said group is of a second logic level, and output gate means responsive to the outputs of the first and second coincidence gate means for delivering an output signal when the data read out of the group of cells is either all of the first logic level or all of the second logic level.

2. The memory device of claim 1 further including inverter means connected between the memory cells and the gate means for selectively inverting the data read out of one of the cells in the group.

3. The memory device of claim 1 wherein the first coincidence gate means comprises an AND gate, the second coincidence gate means comprises a NAND gate, and the output gate means comprises an OR gate.