Dynamic single-transistor memory element for relatively permanent memories

• US 4,055,837 A
• Filed: 10/22/1975
• Issued: 10/25/1977
• Est. Priority Date: 10/22/1974
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Stein, Karl-Ulrich, Horninger, Karlheinrich
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/624,710
• Time in Patent Office: 734 Days
• Field of Search: 340/173 R, 340/173 CA, 307/238, 307/279
• US Class Current: 365/186
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 27/0733 in combination with capacitors only
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

The invention relates to a dynamic single-transistor memory element whereby the information may be stored for long periods of time without an energy supply. The invention also provides for a dynamic single-transistor memory element having the capability of storing two differing information pulses. The write-in process may be effectuated element-wise, line-wise, or matrix-wise. The invention further provides the capability to effectuate the erasure of the information line by line where the information is intermedially stored in the regenerator amplifiers or matrix by matrix where the intermediate storage occurs in the second matrix.

Claims

1. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a pluraliy of selective activation states and said electrode which is not connected with said transistor is connected with said write line.

7. Dynamic single-transistor memory element as defined in claim 1, wherein the write line is galvanically connected with the write lines of the respective elements.

8. Dynamic single-transistor memory element as defined in claim 1, wherein the write line is galvanically connected with the write lines of different group elements of a memory matrix combined in groups.

2. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a plurality of selective activation states and said electrode which is not connected with said transistor is connected with said write line; and

said transistor comprises a MOS field-effect transistor.

9. Dynamic single-transistor memory element as defined in claim 2, wherein the write line is galvanically connected with the write lines of the respective elements.

10. Dynamic single-transistor memory element as defined in claim 2, wherein the write line is galvanically connected with the write lines of different group elements of a memory matrix combined in groups.

3. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a plurality of selective activation states and said electrode which is not connected with said transistor is connected with said write line;

said transistor comprises a MOS field-effect transistor; and

said dielectric of said capacitor comprises two insulator layers.

11. Dynamic single-transistor memory element as defined in claim 3, wherein the write line is galvanically connected with the write lines of the respective elements.

12. Dynamic single-transistor memory element as defined in claim 3, wherein the write line is galvanicaly connected with the write lines of different group elements of a memory matrix combined in groups.

4. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a plurality of selective activation states and said electrode which is not connected with said transistor is connected with said write line;

said transistor comprises a MOS field-effect transistor; and

said capacitor is a MNOS capacitor having a dielectric comprising an SiO₂ layer and an Si₃ N₄ layer.

13. Dynamic single-transistor memory element as defined in claim 4, wherein the write line is galvanically connected with the write lines of the respective elements.

14. Dynamic single-transistor memory element as defined in claim 4, wherein the write line is galvanically connected with the write lines of different group elements of a memory matrix combined in groups.

5. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a plurality of selective activation states and said electrode which is not connected with said transistor is connected with said write line;

said transistor comprises a MOS field-effect transistor;

said capacitor is a MNOS capacitor having a dielectric comprising an SiO₁ layer and an Si₃ N₄ layer; and

said SiO₂ layer has a thickness of 1 through 3 nm.

15. Dynamic single-transistor memory element as defined in claim 5, wherein the write line is galvanically connected with the write lines of the respective elements.

16. Dynamic single-transistor memory element as defined in claim 5, wherein the write line is galvanically connected with the write lines of different group elements of a memory matrix combined in groups.

6. Dynamic single-transistor memory element connected to a word line and a bit line comprising:

a transistor having at least two terminals and a gate terminal, connected at one of said terminals with said bit line and at said gate terminal with said word line;

a capacitor having at least two electrodes connected at one of said electrodes in series to one of said two terminals of said transistor;

wherein said single-transistor memory element comprises a write line, said capacitor is a metal dielectric semiconductor capacitor, said dielectric comprises a plurality of selective activation states and said electrode which is not connected with said transistor is connected with said write line;

said transistor comprises a MOS field-effect transistor; and

said capacitor is a MNOS capacitor having a dielectric comprising an SiO₂ layer having a thickness of 1 to 3 nm and an SiN₄ layer having a thickness of 40 to 60 nm.

17. Dynamic single-transistor memory element as defined in claim 6, wherein the write line is galvanically connected with the write lines of the respective elements.

18. Dynamic single-transistor memory element as defined in claim 6, wherein the write line is galvanically connected with the write lines of different group elements of a memory matrix combined in groups.

19. In a single-transistor memory element connected to a word line and a bit line and comprising a write line, a transistor, and a capacitor having a silicon surface, connected in series thereto, a method of:

switch connecting said transistor for writing-in information via the word line;

applying a negative voltage to said write line for writing-in information through said bit line while using a p-channel transistor as said transistor, such that a flat-band voltage of said capacitor remains constant during storage of information "1" in the memory element and such that said flat-band voltage of said capacitor is sifted (instant t₁) during storage of information "0" in said memory element;

applying a negative read voltage to said capacitor for reading out information through said write line, said read voltage being referenced so that in a case of said stored information "1" an inversion boundary layer is formed at the silicon surface of said capacitor, and in case of said stored information "0" a depletion layer is formed (instant t₂) at said silicon surface at said capacitor; and

applying a positive voltage pulse (instant t₃) to said write line to erase the information stored in said capacitor.

20. A method for the operation of a single-transistor memory element connected to a word line and a bit line and comprising a write line, a transistor, and a capacitor having a silicon surface, connected in series thereto, comprising the steps of:

using a p-channel transistor;

applying a negative voltage to a write line where information in a memory element is stored non-transiently, such that where of an information "0" is stored in said capacitor a shifting of a flat-band voltage occurs and where information "1" is stored the flat-band voltage is held constant; and

erasing the information stored in said capacitor after a read-out operation and before a next write-in operation for non-transient storage by applying a positive voltage pulse to the write line.

21. The method as defined in claim 20, wherein the method further comprises the steps of:

applying said negative voltage to write line for said read-out opeation such that for said stored information "0" a depletion layer is formed at the silicon surface of said capacitor and for said stored information "1" an inversion boundary layer is formed at said silicon surface of said capacitor.

22. The method as defined in claim 20, wherein the method further comprises the steps of:

applying said negative voltage to said write line for read-out operation, where said negative voltage applied has an absolute value greater than two values of the flat-band voltages of the capacitors and integrating it such that the surface potential of said inversion boundary layer, in a case of the constant flat-band voltage of the capacitor adjusts itself to the value of the voltage of the write line less the flat-band voltage, and in a case of the shifted flat-band voltage of the capacitor, it adjusts itself to the value of the voltage present at the write line less the value of the shifted flat-band voltage; and

directing said integrated voltage of the write line to the bit line by way of said transistor for purposes of read-out.

23. The method as defined in claim 20, wherein the method further comprises the step of applying voltages of opposite polarity in a case of using an n-channel transistor as said transistor.