Conditional bypass of error correction for dual memory access time selection

• US 4,058,851 A
• Filed: 10/18/1976
• Issued: 11/15/1977
• Est. Priority Date: 10/18/1976
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation (Unisys Corporation)
• Original Assignee: Sperry Rand Corporation (Unisys Corporation)
• Inventors: Scheuneman, James Herman
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/733,687
• Time in Patent Office: 393 Days
• Field of Search: 364/200, 364/900, 340/173 BB, 235/153 AM
• US Class Current: 714/6.2
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse. Thus, when no error exists in the read data, the RAM is accessed at a relatively fast access time while, if an error exists in the read data, the RAM is accessed at a relatively slower access time to provide the added time required by the ECC to correct the read data.

Claims

1. A conditional bypass error correction system for an addressable main memory, comprising:

memory address register means adapted to receive and store a multibit address for addressing an associated one of an addressable location of a main memory means;

main memory means responsively coupled to said memory address register means and comprising a plurality of addressable locations each of which addressable locations includes a plurality of memory cells in which are stored a plurality of uncorrected read bits and a plurality of associated check bits;

content addressable memory means responsively coupled to said memory address register means and comprising a plurality of content addressable locations each of which includes a plurality of memory cells and in each of which content addressable locations are stored a plurality of address bits that define an address of an addressable location in said main memory means and means associated with said content addressable locations for providing an indication of the comparison of the address bits stored in said memory address register means and the address bits stored in an associated one of said content addressable locations;

error detection and correction logic means coupled to said main memory means and receiving the read bits and the associated check bits from an addressable location addressed by the address stored in said memory address register means for generating corrected read bits therefrom;

interface register means coupled to said main memory means for receiving the uncorrected read bits from said addressed addressable location in said main memory means and coupled to said error detection and correction logic means for receiving the corrected read bits from said error detection and correction logic means;

timing means responsively coupled to said content addressable memory means for coupling a relatively early interface register first gate pulse to said interface register means for coupling said uncorrected read bits into said interface register means if said comparison is a Match condition indicating a determination that the address bits stored in said memory address register means are stored in an associated one of the content addressable locations, or, alternatively, coupling a relatively late interface register second gate pulse to said interface register means for coupling said corrected read bits into said interface register means if said comparison is a Match condition indicating a determination that the address bits stored in said memory address register means are not stored in an associated one of the content addressable locations, said first gate pulse bypassing the error detection and correction operation of said error detection and correction logic means providing a first relatively fast memory access time while said second gate pulse does not bypass the error detection and correction operation of said error detection and correction logic means providing a second relatively slow memory access time, all as determined by said comparison.

2. The system of claim 1 further including:

retry signal generator means responsively coupled to said error detection and correction logic means and said content addressable memory means for generating a retry signal when said error detection and correction logic means determines that there is a correctable error in said uncorrected read bits and said content addressable memory means determines a Match condition;

requestor means responsively coupled to said retry signal for retrying said comparison.

3. The system of claim 2 further including parity error signal generating means responsively coupled to said error detection and correction logic means for coupling a parity error signal to said requestor means when said error detection and correction logic means determines that there is an uncorrectable error in said uncorrected read bits.

4. An error correction system incorporating a content addressable memory, comprising:

main memory means comprising a plurality of addressable locations each of which includes a plurality of memory cells in which are stored a plurality of data bits and a plurality of associated check bits;

memory address register means for receiving and storing a multibit address and coupled to said main memory means for addressing an associated one of the addressable locations of said main memory means;

error correction logic means coupled to said main memory means and receiving the uncorrected data bits and the check bits from an addressable location addressed by the address stored in said memory address register means for generating corrected data bits;

interface register means coupled to said main memory means for receiving the uncorrected data bits from said addressed addressable location in said main memory means and coupled to said error correction logic means for receiving the corrected data bits from said error correction logic means;

content addressable memory means comprising a plurality of content addressable locations each of which includes a plurality of memory cells in which are stored a plurality of address bits that define an address of an addressable location in said main memory means and means associated with said memory cells for providing the alternative Match or Match indications of the comparison of the address bits stored in said memory address register means and the address bits stored in the associated one of said content addressable locations;

timing means coupled to said main memory means for initiating the readout of the addressed memory location in said main memory means; and

,

means coupling said content addressable memory means to said timing means for alternatively gating the uncorrected data bits at a relatively fast memory access time or the corrected data bits at a relatively slow memory access time into said interface register means as a result of said alternative Match or Match indications.

5. The system of claim 4 further including:

retry signal generator means responsively coupled to said error correction logic means and said content addressable memory means for generating a retry signal when said error correction logic means determines that there is a correctable error in said uncorrected data bits and said content addressable memory means determines a Match indication.