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Conditional bypass of error correction for dual memory access time selection

  • US 4,058,851 A
  • Filed: 10/18/1976
  • Issued: 11/15/1977
  • Est. Priority Date: 10/18/1976
  • Status: Expired due to Term
First Claim
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1. A conditional bypass error correction system for an addressable main memory, comprising:

  • memory address register means adapted to receive and store a multibit address for addressing an associated one of an addressable location of a main memory means;

    main memory means responsively coupled to said memory address register means and comprising a plurality of addressable locations each of which addressable locations includes a plurality of memory cells in which are stored a plurality of uncorrected read bits and a plurality of associated check bits;

    content addressable memory means responsively coupled to said memory address register means and comprising a plurality of content addressable locations each of which includes a plurality of memory cells and in each of which content addressable locations are stored a plurality of address bits that define an address of an addressable location in said main memory means and means associated with said content addressable locations for providing an indication of the comparison of the address bits stored in said memory address register means and the address bits stored in an associated one of said content addressable locations;

    error detection and correction logic means coupled to said main memory means and receiving the read bits and the associated check bits from an addressable location addressed by the address stored in said memory address register means for generating corrected read bits therefrom;

    interface register means coupled to said main memory means for receiving the uncorrected read bits from said addressed addressable location in said main memory means and coupled to said error detection and correction logic means for receiving the corrected read bits from said error detection and correction logic means;

    timing means responsively coupled to said content addressable memory means for coupling a relatively early interface register first gate pulse to said interface register means for coupling said uncorrected read bits into said interface register means if said comparison is a Match condition indicating a determination that the address bits stored in said memory address register means are stored in an associated one of the content addressable locations, or, alternatively, coupling a relatively late interface register second gate pulse to said interface register means for coupling said corrected read bits into said interface register means if said comparison is a Match condition indicating a determination that the address bits stored in said memory address register means are not stored in an associated one of the content addressable locations, said first gate pulse bypassing the error detection and correction operation of said error detection and correction logic means providing a first relatively fast memory access time while said second gate pulse does not bypass the error detection and correction operation of said error detection and correction logic means providing a second relatively slow memory access time, all as determined by said comparison.

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