Time-multiplex programmable switching apparatus

• US 4,061,880 A
• Filed: 03/21/1975
• Issued: 12/06/1977
• Est. Priority Date: 03/21/1975
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Dicom Systems Limited
• Inventors: May, George A., Collins, Galen R., Gendo, Indra Lee
• Primary Examiner(s): Brown, Thomas W.
• Application Number:
  US05/560,981
• Time in Patent Office: 991 Days
• Field of Search: 179/15 AT, 179/15 A, 179/15 AL, 179/18 AD, 179/99, 179/15 BA
• US Class Current: 370/382
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

Time-multiplex programmable switching apparatus for establishing on demand time shared connections between pairs of ports. Signals within the system are digital. The invention is described in the context of an electronic private automatic branch exchange (EPABX) telephone system. A central processor unit (CPU) including a recirculating memory carries port address pairs and digital information to be exchanged along with a status word used for identifying program loops. Program steps are sequenced or initiated by timing signals and signaling data from the port units. Common buses interconnect the port units with the central processor unit. Port units are grouped with a common buffer memory for converting parallel data from the CPU to serial form. The CPU memory includes slots for housekeeping functions to detect, inter alia, an off-hook telephone. The principles of the invention are applicable to telephone central offices and digital switching systems as for computers, for example. Individual EPAX'"'"'s may be interconnected for expanded service.

Claims

1. In a telephone system, digital time-multiplex programmable switching apparatus for establishing on demand, time shared connections between pairs of ports comprising

a plurality of port means, each of said port means having a unique address, said port means including means for generating predetermined digital signaling signals in response to particular conditions at said port means and said port means further including means for generating digital information signals in response to an applied information signal,

central processor unit means including memory means having a plurality of recirculating slots including slots for storing pairs of port means addresses and information signals directed to said addresses and means responsive to said signaling signals for inserting in said memory means slots pairs of port means addresses to establish time-multiplex information exchanging connections between said pairs of port means and means responsive to the sequential occurrence of port means addresses in said memory means slots for simultaneously sending digital information stored with each of said port means addresses in said memory means slots to said addressed port means and for receiving digital information from said addressed port means, and

common bus means interconnecting all of said plurality of port means and said central processor means.

2. The combination of claim 1 wherein said received digital information from said addressed port means is applied to shuffler means for storing said digital information until the next occurrence of the memory means slot storing that pair of port means addresses which includes the address of the port means from which said digital information was received and for inserting said stored digital information into said memory means slot with the other of said pair of port means addresses, whereby digital information received from one of the pairs of port means whose addresses are in a particular memory means slot is sent to the other of the pairs of port means at the next occurrence of that time slot.

3. The combination of claim 2 further comprising means in said central processor unit means for controlling the content of said memory means slots in response to signaling signals received from said port means.

4. The combination of claim 3 wherein said means for inserting, further inserts a status derived from said port means signaling signals.

5. The combination of claim 4 wherein said means for controlling the content of said memory means slots is further responsive to said status signal stored in said memory means slots.

6. The combination of claim 5 wherein said means for controlling said memory means slots includes a predetermined program circuit means and said status signal defines a subroutine of a predetermined program.

7. The combination of claim 6 wherein each of said memory means slots comprises a triplet of digital words, each of said triplets including a status word containing said status signal a caller word and a called word, said caller and called words indicating the respective digital addresses of caller and called port means and storing digital information directed to respective port means.

8. In a telephone system, digital time-multiplex programmable switching apparatus for establishing on demand, time shared connections between pairs of ports comprising

a plurality of port means, each of said port means comprising one or more port circuit means having a common buffer memory means, each of said port circuit means having a unique address, said port circuit means including means for generating predetermined digital signaling signals in response to particular condition at said port circuit means and said port circuit means further including means for generating digital information signals when an information input signal is applied,

central processor unit means including memory means having a plurality of recirculating slots and means for inserting in said memory means slots pairs of port circuit means addresses and information signals directed to said addresses in response to said signaling signals from said port circuit means to establish time-multiplex information exchanging connections between said pairs of port circuit means, and

common bus means interconnecting all of said plurality of port means and said central processor means.

9. The combination of claim 8 wherein said buffer memory means receives and transmits data at a first rate and first level of time multiplexing with said central processor unit means and receives and transmits data at a second rate and second level of time multiplexing with said port circuit means.

10. The combination of claim 9 wherein said data path between said buffer memory means and said central processor unit means is parallel and the data path between said buffer memory means and said port circuit means is serial.

11. The combination of claim 8 wherein said means for generating digital information signals when an information input signal is applied is responsive to analog signals and wherein said means further functions to generate analog signals in response to digital information signals.

12. The combination of claim 11 wherein said means for generating digital information signals in response to analog signals and for generating analog signals in response to digital information signals comprises a companded delta modulation coder/decoder.

13. In a telephone system, digital time-multiplex programmable switching apparatus for establishing on demand, time shared connections between pairs of ports comprising

a plurality of port means, each of said port means comprising one or more port circuit means having a common buffer memory means, each of said port circuit means having a unique address, said port circuit means including means for generating predetermined digital signaling signals in response to particular conditions at said port circuit means and said port circuit means further including means for generating digital information signals when an information input signal is applied,

central processor unit means including memory means having a plurality of recirculating slots and means for inserting in said memory means slots pairs of port circuit means addresses and information signals directed to said addresses in response to said signaling signals from said port circuit means to establish time-multiplex information exchanging connections between said pairs of port circuit means and means for controlling the content of said memory means slots in response to signaling signals received from said port circuit means, and

common bus means interconnecting all of said plurality of port means and said central processor means.

14. The combination of claim 13 wherein said buffer memory means receives and transmits data at a first rate and first level of time multiplexing with said central processor unit means and receives and transmits data at a second rate and second level of time multiplexing with said port circuit means.

15. In a telephone system, digital time-multiplex programmable switching apparatus for establishing on demand, time shared connections between pairs of ports comprising

a plurality of port means, each of said port means comprising one or more port circuit means having a common buffer memory means, each of said port circuit means having a unique address, said port means including means for generating predetermined digital signaling signals in response to particular conditions at said port circuit means and said port circuit means further including means for generating digital information signals when an information input signal is applied,

central processor unit means including memory means having a plurality of recirculating slots and means for inserting in said memory means slots pairs of port circuit means addresses and information signals directed to said addresses and status signals in response to said signaling signals from said port circuit means to establish time-multiplex information exchanging connections between said pairs of port circuit means and means for controlling the content of said memory means slots in response to signaling signals received from said port circuit means, and to status signals stored in said memory means slots and to predetermined program circuit means, wherein a status signal defines a subroutine of a predetermined program, and

common bus means interconnecting all of said plurality of port means and said central processor means.

16. The combination of claim 15 wherein said buffer memory means receives and transmits data at a first rate and first level of time multiplexing with said central processor unit means and receives and transmits data a second rate and second level of time multiplexing with said port circuit means.