Digital traffic coordinator
First Claim
1. A coordinator for creating a background cycle and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:
- a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded binary pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N1 and a second code representing a second number N2 upon receipt of input counting pulses at said input means, means for shifting said pulse counter to said number N1 upon receipt of a shift signal and means for creating said shift signal when said pattern progresses to the number N2 ;
means for creating input counting pulses having a frequency corresponding to a desired cycle time;
means for starting said counter upon receipt of an offset signal, said starting means includes a digital device for creating an offset signal at a selected time after a master synchronization pulse from a remote master controller; and
decoding means for creating said selected logic conditions in selected output circuits when said pattern has a selected code corresponding to a number in the range of N1 to N2.
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Accused Products
Abstract
There is provided a coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during the background cycle which cycle and logic conditions are used in governing the signalization of a traffic intersection. This coordinator includes a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99. There is further provided means for controlling the frequency of the counting pulses to a frequency equal to one hundred divided by the time of a desired background cycle in seconds and decoding means for creating the selected logic conditions in output circuits when the counter counts to a selected number in the range of 0 to 99.
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Citations
28 Claims
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1. A coordinator for creating a background cycle and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:
- a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded binary pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N1 and a second code representing a second number N2 upon receipt of input counting pulses at said input means, means for shifting said pulse counter to said number N1 upon receipt of a shift signal and means for creating said shift signal when said pattern progresses to the number N2 ;
means for creating input counting pulses having a frequency corresponding to a desired cycle time;
means for starting said counter upon receipt of an offset signal, said starting means includes a digital device for creating an offset signal at a selected time after a master synchronization pulse from a remote master controller; and
decoding means for creating said selected logic conditions in selected output circuits when said pattern has a selected code corresponding to a number in the range of N1 to N2. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded binary pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N1 and a second code representing a second number N2 upon receipt of input counting pulses at said input means, means for shifting said pulse counter to said number N1 upon receipt of a shift signal and means for creating said shift signal when said pattern progresses to the number N2 ;
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14. A coordinator for creating a background cycle and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:
- a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N1 and a second code representing a second number N2 upon receipt of input counting pulses at said input means;
means for creating input counting pulses having a frequency corresponding to a desired cycle time;
a decoding means for creating said selected logic conditions in selected output circuits when said pattern has a selected code corresponding to a number in the range of N1 to N2 and means for allowing one or more of said selected output circuits to be controlled by a given number in said range. - View Dependent Claims (15, 16, 17, 18, 19, 20)
- a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N1 and a second code representing a second number N2 upon receipt of input counting pulses at said input means;
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21. A coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:
- a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99, and means for controlling the frequency of said counting pulses to 100 divided by the time of a desired background cycle and decoding means for creating one of said logic conditions in one of said output circuits when said counter counts to selected ones of said numbers in the range of 0-99.
- View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. A coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:
- a pulse counter for counting between N1 and N2 in selected fixed increments upon receipt of counting pulses and having output means for creating a distinct signal upon counting to selected evenly distributed increments in the range of N1 to N2, and means for controlling the frequency of said counting pulses to determine the time length of a desired background cycle;
decoding means for creating said selected logic conditions in output circuits when said counter counts to a selected increment in the range of N1 -N2 ; and
, means for allowing one or more of said output circuits to be controlled by a given incremented position in said range.
- a pulse counter for counting between N1 and N2 in selected fixed increments upon receipt of counting pulses and having output means for creating a distinct signal upon counting to selected evenly distributed increments in the range of N1 to N2, and means for controlling the frequency of said counting pulses to determine the time length of a desired background cycle;
Specification