Digital traffic coordinator

• US 4,061,902 A
• Filed: 03/03/1976
• Issued: 12/06/1977
• Est. Priority Date: 03/03/1976
• Status: Expired due to Term

• Current Assignee: Eagle Signal Controls Corp.
• Original Assignee: Gulf & Western Industries Incorporated
• Inventors: Battle, Francis L.
• Primary Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/663,580
• Time in Patent Office: 643 Days
• Field of Search: 307/203, 235/150.24, 340/41 R
• US Class Current: 701/117
• CPC Class Codes: G08G 1/082 Controlling the time between beginning of the same phase of a cycle at adjacent intersections

Abstract

There is provided a coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during the background cycle which cycle and logic conditions are used in governing the signalization of a traffic intersection. This coordinator includes a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99. There is further provided means for controlling the frequency of the counting pulses to a frequency equal to one hundred divided by the time of a desired background cycle in seconds and decoding means for creating the selected logic conditions in output circuits when the counter counts to a selected number in the range of 0 to 99.

Claims

1. A coordinator for creating a background cycle and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:

a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded binary pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N₁ and a second code representing a second number N₂ upon receipt of input counting pulses at said input means, means for shifting said pulse counter to said number N₁ upon receipt of a shift signal and means for creating said shift signal when said pattern progresses to the number N₂ ;

means for creating input counting pulses having a frequency corresponding to a desired cycle time;

means for starting said counter upon receipt of an offset signal, said starting means includes a digital device for creating an offset signal at a selected time after a master synchronization pulse from a remote master controller; and

decoding means for creating said selected logic conditions in selected output circuits when said pattern has a selected code corresponding to a number in the range of N₁ to N₂.

2. A coordinator as defined in claim 1 wherein said number N₁ is 0 and number N₂ is 99 and said pattern changing means includes means to increment by one between 0 and 99.

3. A coordinator as defined in claim 1 including means for creating said shift signal when said pattern has a code corresponding to the number N₂.

4. A coordinator as defined in claim 1 wherein said digital device includes a second pulse counter having an input means for receiving input counting pulses, means for incrementing said counter upon receipt of an input counting pulse, means for starting said second counter by said master synchronization pulse and means for creating said offset signal when said counter reaches a selected number and pulse means for directing pulses to said second counter.

5. A coordinator as defined in claim 4 wherein said pulse means includes means for creating pulses corresponding in frequency with said input counting pulses of said first mentioned counter.

6. A coordinator as defined in claim 4 wherein said digital device counts between a number corresponding to the number N₁ and a number corresponding to the number N₂.

7. A coordinator as defined in claim 6 wherein said pulse means pulses have the same frequency as said input counting pulses of said first mentioned counter.

8. A coordinator as defined in claim 4 wherein said pulse means pulses have the same frequency as said input counting pulses of said first mentioned counter.

9. A coordinator as defined in claim 1 wherein said decoding means includes several sensing means for creating an output signal when said binary pattern exhibits a selected number logic and means for creating a selected logic in an output circuit upon creating of said output signal.

10. A coordinator as defined in claim 9 wherein said output circuit includes a logic gate having a first input controlled by a first logic determined by the logic of said output signal, a second input controlled by a second logic on an enabling terminal on said coordinator and adapted to receive logic from externally of said coordinator and an output line connected to a terminal on said coordinator and having an output logic controlled by said first and second logics.

11. A coordinator as defined in claim 9 wherein first and second of said sensing means control the logic of a single output circuit and including a dual state logic device having an output connected to said single output circuit, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic, means for directing said output signal of said first sensing means to said first means and means for directing said output signal of said second sensing means to said second means.

12. A coordinator as defined in claim 9 wherein first and second of said sensing means control the logic on first and second output circuits, respectively, and including a dual state logic device having an output, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic;

first connecting means for directing said output signal of said first sensing means to said first means;

second connecting means for directing said output signal of said second sensing means to said second means;

a first conductor means for connecting said first means to said first circuit;

a second conductor means for connecting said output to said first circuit;

a third conductor means for connecting said second means to said second output circuit; and

, means for allowing selective interruption of said first or second conductor means.

13. A coordinator as defined in claim 9 including first and second of said sensing means and a logic gate in said coordinator, said gate having a first input means having a first logic controlled by the output signal of the first of said sensing means and a second input means having a second logic controlled by the output signal of the second of said sensing means and an output means for directing a logic to said output circuit and a third logic controlled by first and second logics.

14. A coordinator for creating a background cycle and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:

a pulse counter having an input means for receiving input counting pulses, a codeable output network for creating a coded pattern, means for changing said pattern incrementally and progressively between a first code representing a first number N₁ and a second code representing a second number N₂ upon receipt of input counting pulses at said input means;

means for creating input counting pulses having a frequency corresponding to a desired cycle time;

a decoding means for creating said selected logic conditions in selected output circuits when said pattern has a selected code corresponding to a number in the range of N₁ to N₂ and means for allowing one or more of said selected output circuits to be controlled by a given number in said range.

15. A coordinator as defined in claim 14 wherein said number N₁ is 0 and number N₂ is 99 and said pattern changing means includes means to increment by one between 0 and 99.

16. A coordinator as defined in claim 14 wherein said decoding means includes several sensing means for creating an output signal when said coded binary pattern exhibits a selected number logic and means for creating a selected logic in an output circuit upon creating of said output signal.

17. A coordinator as defined in claim 16 wherein said output circuit includes a logic gate having a first input controlled by a first logic determined by the logic of said output signal, a second input controlled by a second logic on an enabling terminal on said coordinator and adapted to receive logic from externally of said coordinator and an output line connected to a terminal on said coordinator and having an output logic controlled by said first and second logics.

18. A coordinator as defined in claim 16 wherein first and second of said sensing means control the logic of a single output circuit and including a dual state logic device having an output connected to said single output circuit, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic, means for directing said output signal of said first sensing means to said first means and means for directing said output signal of said second sensing means to said second means.

19. A coordinator as defined in claim 16 wherein first and second of said sensing means control the logic on first and second output circuits, respectively, and including a dual state logic device having an output, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic;

first connecting means for directing said output signal of said first sensing means to said first means;

second connecting means for directing said output signal of said second sensing means to said second means;

a first conductor means for connecting said first means to said first circuit;

a second conductor means for connecting said output to said first circuit;

a third conductor means for connecting said second means to said second output circuit; and

, means for allowing selective interruption of said first or second conductor means.

20. A coordinator as defined in claim 16 including first and second of said sensing means and a logic gate in said coordinator, said gate having a first input means having a first logic controlled by the output signal of the first of said sensing means and a second input means having a second logic controlled by the output signal of the second of said sensing means and an output means for directing a logic to said output circuit and a third logic controlled by first and second logics.

21. A coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:

a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99, and means for controlling the frequency of said counting pulses to 100 divided by the time of a desired background cycle and decoding means for creating one of said logic conditions in one of said output circuits when said counter counts to selected ones of said numbers in the range of 0-99.

22. A coordinator as defined in claim 21 including means for starting said pulse counter a selected time after receipt of a master synchronization pulse from a remote master controller.

23. A coordinator as defined in claim 21 wherein said decoding means includes several sensing means for creating an output signal when said coded pattern exhibits a selected number logic and means for creating a selected logic in an output circuit upon creating of said output signal.

24. A coordinator as defined in claim 23 wherein said output circuit includes a logic gate having a first input controlled by a first logic determined by the logic of said output signal, a second input controlled by a second logic on an enabling terminal on said coordinator and adapted to receive logic from externally of said coordinator and an output line connected to a terminal on said coordinator and having an output logic controlled by said first and second logics.

25. A coordinator as defined in claim 23 wherein first and second of said sensing means control the logic of a single output circuit and including a dual state logic device having an output connected to said single output circuit, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic, means for directing said output signal of said first sensing means to said first means and means for directing said output signal of said second sensing means to said second means.

26. A coordinator as defined in claim 23 wherein first and second of said sensing means control the logic on first and second output circuits, respectively, and including a dual state logic device having an output, a first means for shifting said output of said dual state logic device to a first binary logic and a second means for shifting said output of said dual state logic to a second binary logic opposite to said first binary logic;

first connecting means for directing said output signal of said first sensing means to said first means;

second connecting means for directing said output signal of said second sensing means to said second means;

a first conductor means for connecting said first means to said first circuit;

a second conductor means for connecting said output to said first circuit;

a third conductor means for connecting said second means to said second output circuit; and

, means for allowing selective interruption of said first or second conductor means.

27. A coordinator as defined in claim 23 including first and second of said sensing means and a logic gate in said coordinator, said gate having a first input means having a first logic controlled by the output signal of the first of said sensing means and a second input means having a second logic controlled by the output signal of the second of said sensing means and an output means for directing a logic to said output circuit and a third logic controlled by first and second logics.

28. A coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during said background cycle, said cycle and logic conditions being used in governing the signalization of a traffic intersection, said coordinator comprising:

a pulse counter for counting between N₁ and N₂ in selected fixed increments upon receipt of counting pulses and having output means for creating a distinct signal upon counting to selected evenly distributed increments in the range of N₁ to N₂, and means for controlling the frequency of said counting pulses to determine the time length of a desired background cycle;

decoding means for creating said selected logic conditions in output circuits when said counter counts to a selected increment in the range of N₁ -N₂ ; and

, means for allowing one or more of said output circuits to be controlled by a given incremented position in said range.