Wideband frequency multiplier particularly adapted for use in badge readers and the like

• US 4,063,070 A
• Filed: 11/12/1976
• Issued: 12/13/1977
• Est. Priority Date: 04/01/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Verhaeghe, Michel Paul, Delarue, Gerard Jean-Marie
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US05/741,254
• Time in Patent Office: 396 Days
• Field of Search: 328/15, 235/61.11 D, 235/61.12 M, 235/61.7 B, 360/51, 360/2
• US Class Current: 235/474
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: G11B 27/30 on the same track as the main recording
• CPC Class Codes: H03K 3/72 with means for varying repetition rate of trains
• CPC Class Codes: H03K 3/78 Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
• CPC Class Codes: H03K 5/156 Arrangements in which a continuous pulse train is transformed into a train having a desired pattern

Abstract

An improved wideband frequency multiplier characterized as follows: a saw-tooth signal generator supplying a saw-tooth wave having a frequency equal to the frequency to be multiplied, the level of the voltage wave varying between a reference level and a maximum which is related to the frequency to be multiplied; storage means for storing a voltage equal to, or closely approaching the maximum voltage value of the saw-tooth wave; a voltage divider having several outputs, each of which provides an output which is a given fraction of the stored voltage; a number of comparators each of which corresponds to and is coupled to an output of the voltage divider, each comparator comparing the instantaneous value of the saw-tooth voltage with the voltage supplied by the corresponding output of the voltage divider, and supplying a first level signal when said instantaneous value is lower than the voltage supplied by said corresponding output, and a second level signal when it is higher; and logical circuits combining the signals supplied by the comparators so as to give an output signal the frequency of which is a given multiple of the frequency of the saw-tooth signal.

A timing circuit for a badge reader, or the like where the data is magnetically NRZ recorded on, or in, the badge, or the like. The timing circuit employs a frequency doubler as generally described above. The timing circuit also utilizes at least one additional logic circuit. The timing circuit provides timing signals synchronized with the reading of the data from the badge or the like.

Claims

1. A frequency multiplier including in combination the following structural elements:

sawtooth signal generator means producing a sawtooth linear voltage with a frequency equal to the frequency to be multiplied, the magnitude of the sawtooth linear voltage varying between a reference magnitude and a maximum magnitude which is mathematically related to the frequency to be multiplied;

a storage device coupled to said sawtooth signal generator means for a storing voltage having a magnitude equal to said maximum magnitude;

a voltage divider coupled to said sawtooth signal generator means and said storage device, said voltage divider including a plurality of outputs, each of said outputs electrically manifesting a voltage magnitude which is a predetermined fraction of the maximum magnitude stored voltage stored by said storage device;

a number of comparators, each comparator being associated with one of the outputs of the voltage divider and coupled to said sawtooth signal generator means, each comparator comparing the instantaneous magnitude of the sawtooth voltage with the magnitude of the voltage manifested at its associated voltage divider output, each comparator supplying a first level signal when the sawtooth voltage is higher in magnitude than the magnitude of the voltage manifested at its associated divider output and, a second level signal when the sawtooth voltage is lower in magnitude than the magnitude of the voltage manifested at its associated divider output; and

logic circuit means, coupled to said number of comparators, said logical circuit means logically combining the signals from said number of comparators to provide an output signal the basic time-period of which is a given sub-multiple of the time-period of the sawtooth signal.

2. A frequency multiplier according to claim 1, further characterized in that said sawtooth signal generator means includes a pulse generator for producing pulse pairs, each pulse of each pulse pair being closely displaced in time one to another, the frequency of each pulse pair being equal to the frequency to be multiplied, the first pulse in each pulse pair controlling the storage of the maximum magnitude of the sawtooth voltage by said storage device, and the second pulse in each pulse pair controlling the return of the sawtooth voltage to the reference magnitude by the sawtooth generator means.

3. A frequency multiplier according to claim 2, further characterized in that the storage device is comprised of a capacitor and an electronic switch, said capacitor receiving the sawtooth voltage via said electronic switch during the time period of the first pulse in each pulse pair.

4. A frequency multiplier according to claim 3, further characterized in that the electronic switch is a field effect transistor switch.

5. A frequency multiplier according to claim 3, further characterized in that the electronic switch is a bipolar transistor switch.

6. A frequency multiplier according to claim 3, further characterized in that said pulse generator has an input terminal adapted to receive a signal the frequency of which is to be multiplied, said signal the frequency of which is to be multiplied being formed of a series of input pulses, said input pulses having a repetition frequency constituting the frequency to be multiplied, and said pulse generator in response to each said input pulse forms and provides one of said pulse pairs.

7. A timing signal generator receiving data pulses with a time position which depends on a basic cycle of variable duration, a pulse being received at the beginning of each cycle and in the middle of at least one of said cycles, said timing generator producing a series of timing oscillations each said timing oscillation having a time period which is equal to one-half of one of said cycles, said timing signal generator comprising in combination the following structural elements:

a frequency doubler according to claim 6, wherein the voltage divider includes among said plurality of outputs, a three quarter output for electrically manifesting a voltage whose magnitude is three quarters of the maximum magnitude stored voltage stored by said storage device, the three-quarter comparator and said logic circuit means associated with said three quarter output providing a first signal during the last quarter of each of said time periods; and

a two input AND logic circuit for receiving said first signal from said three-quarters comparator and said logic circuit means and said data pulses, said two input AND logic circuit producing an output signal when a data pulse is coincident with said first signal, said AND logic circuit output being utilized as the input to the frequency doubler.

8. A frequency multiplier particularly adapted to respond to a variation in the pulse repetition rate between successive pulses of an input pulse train having a pulse repetition rate subject to variation, said frequency multiplier including:

sawtooth voltage generator means responsive to said input pulse train having a repetition rate subject to variation, said sawtooth voltage generator means providing a sawtooth voltage waveform wherein the maximum voltage magnitude of each sawtooth bears a direct fixed mathematical relationship to the repetition rate of predetermined first and second ones of said pulses of said input pulse train;

voltage storage means coupled to said sawtooth generator means, said voltage storage means successively sensing and storing the maximum voltage magnitude of each successive sawtooth of said sawtooth voltage waveform;

voltage comparison means coupled to sawtooth voltage generator means and said voltage storage means, said voltage comparison means successively comparing the successive magnitudes of the voltage stored in said storage means with the instantaneous voltage value of the sawtooth following in time the sawtooth whose maximum voltage magnitude is stored in said storage means;

logical circuit means coupled to said voltage comparison means, said logical circuit means being response to said voltage comparison means to provide an output pulse train having a repetition rate bearing a fixed predetermined mathematical relationship with the pulse repetition rate of said input pulse train, whereby the pulse repetition rate of said output pulse train tracks the pulse repetition rate of said input pulse train.

9. A frequency multiplier as recited in claim 8 wherein the sawtooth generator means comprises:

a first single shot circuit having an input and an output, said input of said first single shot circuit being adapted to receive said input pulse train;

a second single shot circuit having an input and an output, said input of said second single shot circuit being connected to said output of said first single shot circuit;

a third single shot circuit having an input and an output, said input of said third single shot circuit being connected to said output of said second single shot circuit;

a sawtooth signal generator including a transistor having a collector, base and emitter, the collector of said transistor being connected to a current source, the base of said transistor being connected to said output of said third single shot circuit and the emitter of said transistor being connected to a source of reference potential, a capacitor connected between said collector of said transistor and said source of reference potential, said sawtooth signal generator having an output terminal connected to the common juncture of said collector of said transistor and said capacitor.

10. A frequency multiplier as recited in claim 9 wherein the voltage storage means comprises:

a first amplifier having a positive input, a negative input, and an output;

a second amplifier having a positive input, a negative input and an output;

an electronic switch having an input connected to the output of said first amplifier, a control input connected to the output of said first single shot circuit and an output connected to the positive input of said second amplifier;

a capacitor connected between said output of said electronic switch and said source of reference potential;

first connection means directly connecting said positive input of said first amplifier with said output terminal of said sawtooth signal generator;

said voltage storage means having an output terminal;

and second connection means directly connecting in common said output of said second amplifier, said negative input of said second amplifier, said negative input of said first amplifier and said output terminal of said voltage storage means.

11. A frequency multiplier as recited in claim 10 wherein the voltage comparison means comprises:

a resistor having at least first and second taps, said resistor being connected between said output terminal of said voltage storage means and said source of reference potential;

at least first and second comparison circuits, each comparison circuit having a first input, a second input and an output;

third connection means connecting in common said first input of said first comparison circuit, said first input of said second comparison circuit and said output of said sawtooth signal generator;

and second connection means respectively connecting said second input of said first comparison circuit to said first tap on said resistor, and said second input of said second comparison circuit to said second tap on said resistor.

12. A frequency multiplier as recited in claim 11 wherein said logical circuit means has at least two inputs respectively connected to said outputs of said at least two comparison circuits and at least one output at which said output pulse train is electrically manifested.

13. In a reader for reading magnetically encoded data on a record medium, where the reading of the magnetically encoded data requires relative motion between the record medium and a reading means, and the relative motion is subject to wide variation in the rate of movement, the provision of a timing circuit responsive to data read by said reading means to provide timing signals bearing a fixed time relationship to the reading of said data, said timing circuit comprising:

a logical AND circuit having at least a first input, a second input and an output;

a frequency doubler circuit in accordance with claim 8 wherein said doubler circuit includes an input for receiving said input pulse train having a pulse repetition rate subject to variation, a first output for providing said output pulse train having a pulse repetition rate bearing a fixed mathematical relationship with the pulse repetition rate of said input train, said frequency doubler circuit further including additional means for providing a further pulse train having a pulse repetition rate bearing a second fixed mathematical relationship with the pulse repetition rate of said input train;

a logical AND circuit having a first input adapted to receive signals representative of said data read by said reading means, a second input adapted to receive said further pulse train from said frequency doubler circuit, and an output for providing said input pulse train to the said input of said frequency doubler circuit;

whereby said output pulse train constitutes said timing signals which are continuously synchronized with the reading of the encoded data from the record medium.

14. In a reader for reading magnetically encoded data on a record medium as recited in claim 13 where said read medium is an identification badge, entry badge, or the like and said magnetically encoded data carried by said badge, or the like is magnetically encoded in accordance with the known non-return to zero method of magnetically encoding data.

15. In a reader for reading magnetically encoded data on a record medium, where the reading of the magnetically encoded data requires relative motion between the record medium and a reading means, and the relative motion is subject to wide variation in the rate of movement, the provision of a timing circuit responsive to data read by said reading means to provide timing signals bearing a fixed time relationship to the reading of said data, said timing circuit comprising:

a logical AND circuit having at least a first input, a second input and an output;

a frequency doubler circuit in accordance with claim 12 wherein said doubler circuit includes an input for receiving said input pulse train having a pulse repetition rate subject to variation, a first output for providing said output pulse train having a pulse repetition rate bearing a fixed mathematical relationship with the pulse repetition rate of said input train, said frequency doubler circuit further including additional means for providing a further pulse train having a pulse repetition rate bearing a second fixed mathematical relationship with the pulse repetition rate of said input train;

a logical AND circuit having a first input adapted to receive signals representative of said data read by said reading means, a second input adapted to receive said further pulse train from said frequency doubler circuit, and an output for providing said input pulse train to the said input of said frequency doubler circuit;

whereby said output pulse train constitutes said timing signals which are continuously synchronized with the reading of the encoded data from the record medium.

16. In a reader for reading magnetically encoded data on a record medium, where the reading of the magnetically encoded data requires relative motion between the record medium and a reading means, and the relative motion is subject to wide variation in the rate of movement, the provision of a timing circuit responsive to data read by said reading means to provide timing signals bearing a fixed time relationship to the reading of said data, said timing circuit comprising:

a logical AND circuit having at least a first input, a second input and an output;

frequency doubler circuit means, said frequency doubler circuit means includes, an input for receiving an input pulse train having a pulse repetition rate subject to variation, a first output for providing an output pulse train having a pulse repetition rate bearing a fixed mathematical relationship with the pulse repetition rate of said input train, said frequency doubler circuit means further including additional means for providing a further pulse train having a pulse repetition rate bearing a second fixed mathematical relationship with the pulse repetition rate of said input train;

a logical AND circuit having a first input adapted to receive signals representative of said data read by said reading means, a second input adapted to receive said further pulse train from said frequency doubler circuit means, and an output for providing said input pulse train to the said input of said frequency doubler circuit means;

whereby said output pulse train constitutes said timing signals which are continuously synchronized with the reading of the encoded data from the record medium.