Asynchronously operating signal diagnostic system for a programmable machine function controller

• US 4,063,311 A
• Filed: 08/17/1976
• Issued: 12/13/1977
• Est. Priority Date: 08/17/1976
• Status: Expired due to Term

• Current Assignee: Cincinnati Machines Incorporated (Fives SA)
• Original Assignee: Cincinnati Machines Incorporated (Fives SA)
• Inventors: Schubeler, Kenneth Erwin, Kline, Eric Randall, Jeremiah, Edward Scott
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/715,133
• Time in Patent Office: 483 Days
• Field of Search: 340/172.5, 445/1, 235/151.1, 235/151.11, 235/153 A, 235/153 AC, 235/153 AK, 235/151.3
• US Class Current: 714/25
• CPC Class Codes: G05B 19/058 Safety, monitoring
• CPC Class Codes: G05B 2219/14112 Diagnostic, troubleshooting

Abstract

A diagnostic apparatus for use with a programmable machine function controller having a memory for storing a machine control program wherein the controller continuously scans the memory and generates output signals in response to input signals having signal states corresponding to the desired states as defined by the machine control program. The diagnostic apparatus includes a second program for testing the input signals as they are required by the machine control program to execute cycle steps and cycles of operation relative to the machine. The diagnostic apparatus operates asynchronously with the machine function controller to sequentially check the cycles of operation, many of which may be occurring simultaneously. In checking each cycle of operation, the diagnostic apparatus checks each cycle step and further checks the state of each input signal associated with each cycle step. The diagnostic apparatus is operative to continuously display a representation of the failure conditions detected. Finally, the apparatus detects and displays a representation of input signal failures which are independent of any of the cycles of operation associated with the machine.

Claims

1. A programmable machine function controller of the type comprised in part of a memory having a first section containing a machine control program representing at least one cycle of operation associated with a machine, said cycle of operation being comprised of a number of cycle steps and each cycle step being defined by a number of cycle input signals, said machine control program defining the states of output signals being generated to a contact bus in electrical communication with the machine in response to predetermined states of the input signals, and said controller further comprising means for continuously and iteratively reading the memory and a logic circuit responsive to the memory for controlling the states of the output signals as a function of the actual input signal states corresponding to the input signal states defined by the program, wherein the improvement comprises:

a. a second section of said memory for storing a first diagnostic program defining a test of error states of selected cycle input signals associated with the particular cycle steps defining the machine cycles of operation, said diagnostic program being stored in the memory for controlling the testing of the states of the selected cycle input signals;

b. means operating asynchronously with the controller for generating a first input signal to initiate a test of one of the machine cycles of operation;

c. means responsive to the controller and the generating means for detecting a first output signal representing a particular cycle step in the one of the machine cycles of operation;

d. means responsive to the controller and the generating means for detecting a second output signal representing an error state of one of the selected cycle input signals as defined by the first diagnostic program; and

e. means having inputs responsive to the first input signal and the first and second output signals for displaying a representation of the inputs.

2. The controller of claim 1 wherein the improvement further comprises:

a. a third section of said memory for storing a second diagnostic program defining a test of error states of noncycle input signals independent of any machine cycle of operation, said second diagnostic program being stored in the memory for controlling the testing of the states of the noncycle input signals;

b. means responsive to the generating means and connected to the controller for providing a second input signal to initiate a test of the noncycle input signals;

c. means responsive to the providing means and the controller for detecting a third output signal representing an error state of one of the noncycle input signals as defined by the second diagnostic program and

d. means having inputs responsive to the second input signal and a third output signal and an output connected to the displaying means for causing the displaying means to display a representation of the second input signal and the third output signal.

3. The controller of claim 15, wherein the second section of said memory further comprises:

a. a first storage area for storing a first program operating in conjunction with the controller for producing the first output signal, said first output signal being generated in response to the simultaneous occurrence of the first input signal and a third input signal representing a cycle step associated with the cycle of operation being tested; and

b. a second storage area for storing a second program operating it in conjunction with the controller for producing the second output signal, said second output signal being generated in response to the simultaneous occurrence of the first and third input signals and a cycle input signal being in an error state as defined by the second program.

4. The controller of claim 3, wherein the means for generating the first input signal further comprises:

a. a cycle counter operating asynchronously with the controller for continuously and sequentially producing a set of cycle numbers, each cycle number having a duration approximately equal to the time required by the controller to read the memory one time, said cycle counter further producing a last cycle number signal; and

means responsive to the cycle counter and the contact bus for comparing the cycle numbers with numbers corresponding to addresses on the contact bus and producing the first input signal in response to detecting an equality therebetween.

5. The controller of claim 4, wherein the means for detecting the first output signal further comprises:

a buffer store responsive to each cycle number and the first output signal and connected to the contact bus for storing a cycle step number corresponding to the first output signal; and

b. means responsive to the contact bus and the buffer store for comparing the stored cycle step number with numbers corresponding to addresses occurring on the contact bus and generating another input signal to the controller in response to an equality therebetween.

6. The controller of claim 5, wherein the means for detecting the second output signal further comprises:

a. an input cycle counter responsive to the first output signal for sequentially producing cycle input numbers;

b. means responsive to the second output signal for comparing each cycle input number with a number corresponding to the address of the second output signal to produce a latch signal in response to an equality therebetween;

c. means responsive to the latch signal for producing a first timing signal of a predetermined duration;

d. means responsive to the first timing signal and connected to the input cycle counter for inhibiting the operation of the input cycle counter for the predetermined duration thereby maintaining the cycle input number corresponding to the second output signal.

7. The controller of claim 6, wherein the input cycle counter further produces a final number for causing the cycle counter to increment from its current counter state to a successive counter state.

8. The controller of claim 7, wherein the display means further comprises a first latching means responsive to the latch signal for storing the current cycle number, cycle step number and cycle input number.

9. The controller of claim 16, wherein the third section of said memory further comprises a third storage area for storing a third program operating in conjunction with the controller for producing a third output signal, said third output signal being generated in response to the simultaneous occurrence of the second input signal and one of the noncycle input signals being in an error state as defined by the third program.

10. The controller of claim 9, wherein the providing means further comprises:

a. noncycle counter means responsive to the last cycle number signal for sequentially producing a set of noncycle numbers; and

b. means responsive to the noncycle counter means and the controller for comparing the noncycle numbers with numbers corresponding to addresses on the contact bus to produce the second input signal in response to an equality therebetween.

11. The controller of claim 10, wherein the means for detecting the third output signal further comprises:

a. a noncycle input counter responsive to the third output signal for sequentially producing a number of noncycle input numbers;

b. means responsive to the third output signal for comparing each noncycle input number with numbers corresponding to the address of the third output signal to produce a noncycle latch signal in response to an equality therebetween;

c. means responsive to the noncycle latch signal for producing a second timing signal of the predetermined duration;

d. means responsive to the second timing signal and connected to the noncycle input counter to inhibit the operation of the noncycle input counter for the predetermined duration thereby maintaining the noncycle input number corresponding to the third output signal; and

e. means responsive to the noncycle latch signal and connected to said first latching means for disabling the output of the first latching means for the duration of the noncycle latch signal.

12. The controller of claim 11, wherein the causing means further comprises second latching means connected to the noncycle input counter and the noncycle counter means and responsive to the noncycle latch signal for storing the noncycle number and noncycle input number occurring at the time of the noncycle latch signal.

13. The controller of claim 12, wherein the displaying means is connected to the first and second latching means and further comprises:

a. a most significant decimal digital display responsive to the cycle number;

b. a second least significant decimal digital display selectively responsive to the cycle step number and the noncycle number as a function of the noncycle latch signal; and

c. a least significant decimal digital display selectively responsive to the cycle input number and the noncycle input number as a function of the noncycle latch signal.

14. The controller of claim 13, wherein the noncycle counter means further produces a reset signal for resetting the disabling means, the first and second latching means and the cycle counter whereby the cycle counter may then be incremented to its initial state resulting in an iteration of the diagnostic cycle.