Digital load control circuit and method for power monitoring and limiting system

• US 4,064,485 A
• Filed: 07/22/1976
• Issued: 12/20/1977
• Est. Priority Date: 07/22/1976
• Status: Expired due to Term

• Current Assignee: Butler Manufacturing Company (Bluescope Steel Limited)
• Original Assignee: Pacific Technology Corp.
• Inventors: Leyde, Warren L.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/707,564
• Time in Patent Office: 516 Days
• Field of Search: 340/409, 340/419, 340/147 R, 340/150, 340/151, 340/152, 235/151.21, 235/151.2, 235/151.1, 322/8, 322/25, 322/36, 323/1, 323/2, 323/66, 307/31, 307/34, 307/35, 307/38, 307/126, 307/140, 307/152
• US Class Current: 307/39
• CPC Class Codes: G01R 21/00 Arrangements for measuring electric power or power factor G01R7/12 takes precedence
• CPC Class Codes: H02H 3/033 with several disconnections in a preferential order, e.g. following priority of the users, load repartitionH02H3/06 takes precedence
• CPC Class Codes: H02J 3/14 by switching loads on to, or off from, network, e.g. progressively balanced loading
• CPC Class Codes: Y02B 70/3225 Demand response systems, e.g. load shedding, peak shaving
• CPC Class Codes: Y04S 20/222 Demand response systems, e.g. load shedding, peak shaving

Abstract

To maintain power consumption within predetermined limits, the ON/OFF states of a plurality of electrical loads are controlled by a digital load control circuit that forms part of a closed-loop control system. The power consumed by the ON loads is monitored and compared with a reference and in response to such comparison command signals are produced that instruct the digital circuit to add or shed loads as required, to increase or decrease, respectively, the power consumption. Inputs to the load-control circuit are in the form of one or more add or shed command pulses wherein the former instructs the circuit to add a load, and the latter instructs the circuit to shed a load. To execute these commands, the load-control circuit includes a reversible, recycling address generator that successively addresses a bank of addressable latches, one for controlling the ON/OFF state of each load. As the latches are successively addressed, logic circuitry operates to detect a concurrence of an add command and an OFF load state at the addressed latch, or a concurrence of a shed command and an ON load state at the addressed latch. Detection of the former set of conditions causes the then addressed latch to be switched from its load OFF state to its ON state and detection of the latter set of conditions causes the then addressed latch to be switched from its load ON state to its OFF state. Various embodiments of the foregoing are disclosed including circuitry for selectively dividing the plurality of loads into two different groups, one of which is a fixed priority group wherein the loads thereof are added and shed in a fixed order, and the other of which is a rotate group wherein the order that the loads are added and shed is rotated so that all of the loads of such group equally share the available ON time; and circuitry for selecting a limit to the total number of rotate loads that can be ON at any given time and a limit to the number of such loads that can be OFF at any given time.

Claims

1. A circuit for controlling the the "on/off" states of each of a plurality of electrical loads in response to power monitoring and signal generating circuit means that monitors the electrical power delivered to the "on" loads and produces an add control signal commanding the addition of one or more of the loads when power consumption is to be increased and produces a shed control signal commanding the shedding of one or more of said plurality of loads when such power consumption is to be decreased, comprising:

a plurality of individually addressable load control latch means, each having a load-off state and a load-on state, said plurality of load control latch means having a common data input means to which each of said load control latch means is individually responsive when it is addressed, each of said plurality of loads being adapted for control by a separate one of said load control latch means so that when each of said latch means is in its load-off state the load controlled thereby is "off", and when each of said latch means is in its load-on state, the load controlled thereby is "on";

address generating means for generating a succession of address signals, each such signal being effective to address a separate one of said plurality of load control latch means;

multiplexing means responsive to said succession of address signals produced by said address generator means so as to be synchronously operated with the addressing of said load control latch means, said multiplexing means having a plurality of inputs each of which is connected to a separate one of said plurality of load control latch means, said multiplexing means having a common output at which a signal is produced indicating the state of that one of said load control latch means then being addressed by said counter means;

add detection logic circuit means for detecting concurrence of a first set of conditions comprising the occurrence of the add control signal and the occurrence of a signal at said output of said multiplexing means indicating that the one of said load control latch means then being addressed is in its load-off state;

shed logic detection means for detecting concurrence of a second set of conditions comprising the occurrence of the shed control signal and a signal at said output of said multiplexing means indicating that the one of said load control latch means then being addressed is in its load-on state; and

means connecting said add logic detection means and said shed logic detection means to said data input means of said plurality of load control latch means for responding to the detection by said add logic detection means of the concurrence of said first set of conditions to switch that one of said load control latch means then being addressed to said load-on state, and for responding to the detection by said shed logic detection means of the concurrence of said second set of conditions to switch that one of said load control latch means then being addressed to said load-off state.

2. The circuit set forth in claim 1, wherein said add and shed control signals are in the form of pulses, each add pulse signal commanding that one load be added and each shed pulse signal commanding that one load be shed, and further comprising:

add latch means having first and second states, said add latch means when in its first state being responsive to said add control signal to assume its second state;

shed latch means having first and second states, said shed latch means when in its first state being responsive to said shed control signal to assume its second state;

said add detection logic means being connected to said add latch means and being responsive to said occurrence of said add control signal by responding to said add latch means being in its second state;

said shed detection logic means being connected to said shed latch means and being responsive to said occurrence of said shed control signal by responding to said shed latch means;

add latch reset means for resetting said add latch means from its second state to its first state in response to said add logic detection means detecting said concurrence of said first set of conditions; and

shed latch reset means for resetting said shed latch means from its second state to its first state in response to said shed logic detection means detecting said concurrence of said second set of conditions.

3. The circuit of claim 2 wherein said address generating means includes means for cyclically generating said succession of address signals, and further comprises execute logic circuit means connected to said add and shed latch means and to said add and shed detection logic means and to said address generating means, said execute logic circuit means preventing said add and shed detection logic means from responding to said add and shed latch means being in their second states until the beginning of a cycle of said address generating means.

4. The circuit of claim 1 for controlling the "on/off" states of the plurality of loads in a predetermined fixed priority sequence, wherein:

said address generating means includes means for cyclically generating said succession of address signals and means for enabling said address generating means to selectively assume forward and reverse directions of operation in which said address signals are generated in a forward direction of succession and a reverse direction of succession, respectively; and

direction control circuit means for disposing said address generating means in said forward direction of operation in response to said add control signal and for disposing said address generating means in its reverse direction of operation in response to said shed control signal, whereby the plurality of loads are added in response to the add control signal in a sequence determined by the forward direction of succession of said address signals and are shed in response to the second control signal in a sequence determined by the reverse direction of succession of said address signals.

5. The circuit of claim 1 for controlling the "on/off" states of the plurality of electrical loads in which available electrical power is to be distributed to the "on" loads on a rotated basis, and further comprising:

logic circuit means for operating said address generating means and said add and shed detection logic circuit means so as to enable said add detection logic circuit means to detect the concurrence of said first set of conditions when that one of said load control latch means is addressed that had been the earliest to be switched to its load-off state and so as to enable said shed logic detection means to detect the concurrence of said second set of conditions when that one of said load control latch means is addressed that had been the earliest to be switched to its load-on state.

6. The circuit of claim 5, wherein said logic circuit means comprises a last load state logic circuit means responsive to said output of said multiplexing means for memorizing the state of the last one of said load control latch means that has been addressed, said last load state logic circuit means being effective to enable said add detection logic circuit means to detect the concurrence of said first set of conditions when the first one of said control latch means that is addressed after at least one of said load control latch means that is in its load-on state has been addressed or when all of said load control latch means are in the load-off states, and said last load state logic circuit means being effective to enable said shed detection logic circuit means for detecting the concurrence of said second set of conditions when the first one of said load control latch means that is addressed after at least one of said load control latch means that is in its load-off state has been addressed or when all of said load control latch means are in the load-on states.

7. The circuit of claim 5, wherein said logic circuit means comprises:

address memory circuit means for memorizing the address signal for the last load control latch means that has been switched between its states; and

means responsive to the alternative conditions of either all of said load control latch means being in their load-on states or all of said load control latch means being in their load-off states for causing said address generating means to commence generating said address signals with that address signal that has been memorized by said address memory circuit means.

8. The circuit of claim 1 for controlling one group of the plurality of loads as a first-type of loads and for controlling another group of the plurality of loads as a second-type of loads, the group of first-type loads having a different predetermined "on/off" switching sequence in response to said first and second control signals than that of the group of second-type loads, and further comprising:

load-type selection and decoding circuit means responsive to said address signals from said address generating means for enabling each of said plurality of load control latch means to be selected for operating the load controlled thereby as a first-type or as a second-type of load, said load-type selection and decoding circuit means being responsive to each said address signal to produce a signal synchronously therewith indicating the selected type of the load controlled by the load control latch means then being addressed;

mode determining circuit means responsive to said load-type selection and decoding circuit means and to said multiplexing means and having a first electrical condition indicating that said add and shed control signals are to act on one of the group of loads of the first-type and having a second electrical condition indicating that said add and shed control signals are to act on one of the group of loads of the second-type;

said add and shed detection logic circuit means including logic means for enabling the detection of concurrence of said first and second sets of conditions, respectively, when said load-type selection and decoding circuit means produces a signal indicating that the addressed load-control latch means controls one of the loads of the first-type and said mode determining circuit means is in its first electrical condition and when said load type selection and decoding circuit means produces a signal indicating that the addressed load control latch means controls one of the loads of the second-type and said mode determining circuit means is in its second electrical condition.

9. The circuit of claim 8 for controlling the group of first-type loads on a rotated switching sequence so that available electrical power is distributed to the "on" loads on a non-priority time sharing basis, and further comprising:

logic circuit means for operating said address generating means and said add and shed detection logic circuit means so as to enable said add detection logic circuit means to detect the concurrence of said first set of conditions when that one of said load control latch means is addressed that had been the earliest to be switched to its load-off state and so as to enable said shed logic detection means to detect the concurrence of said second set of conditions when that one of said load control latch means is addressed that had been the earliest to be switched to its load-on state.

10. The circuit of claim 9 for controlling the group of second-type loads on a fixed priority switching sequence, and further comprising:

logic circuit means for operating said address generating means in forward and reverse directions of address signal succession in response to said add and shed control signals, respectively, so as to enable said add detection logic circuit means to detect the concurrence of said first set of conditions when said address generating means is in said forward direction of address signal succession and so as to enable said shed detection logic circuit means to detect the concurrence of said second set of conditions when said address generating means is in said reverse direction of address signal succession.

11. The circuit of claim 1 for controlling the "on/off" states of the plurality of loads on a rotational basis, and further comprising:

simulated add and shed control signal generating means for generating control signals that simulate the add and shed control signals for causing one of said load control latch means to be switched to its load-on state and another of said load control latch means to be switched to its load-off state thereby rotating the "on/off" states of the plurality of loads; and

counting means responsive to said multiplexing means for counting the number of said load control latch means that in their load-off state, said simulated control signal generating means being responsive to said counting means for generating said control signals that simulate the add and shed control signals when a predetermined number of said load control latch means in their load-off state have been counted.

12. The circuit of claim 1 for controlling the plurality of loads so that the number of such loads that can be switched to the "on" state has a preset limit, and further comprising:

add inhibiting logic circuit means that when operative prevents said add detection logic circuit from detecting said concurrence of said first set of conditions; and

counting circuit means for counting the number of said load control latch means which when addressed are in predetermined one of their states, said add inhibiting logic circuit means being normally inoperative and being responsive to said counting circuit means to become operative when said counting circuit means counts a predetermined number of said load control latch means that are in said predetermined one of their states.

13. The circuit of claim 1 for controlling the plurality of loads so that the number of such loads that can be switched to the "off" state has a preset limit, and further comprising:

shed inhibiting logic circuit means that when operative prevents said shed detection logic circuit means from detecting said concurrence of said second set of conditions; and

counting circuit means for counting the number of said load control latch means then when addressed are in a predetermined one of their states, said shed inhibiting logic circuit means being normally inoperative and being responsive to said counting circuit means to become operative when said counting circuit means counts a predetermined number of said load control latch means in said predetermined one of their states.

14. The circuit of claim 10, wherein said mode determining means includes group priority selection means for establishing an intergroup priority in the adding and shedding of the ends of the first-type group with respect to the loads of the second-type group.

15. The circuit of claim 10 wherein said address generating means has a forward operating direction in which said address signals are generated in a predetermined sequence and a reverse operating direction in which said address signals are generated in the reverse of said sequence, and wherein said load-type selector and decode means is predisposed so that all of the first-type of loads are controlled by load control latch means addressed by consecutive address signals and so that said second-type loads are controlled by the remaining load control latch means, and wherein said mode determining means comprise a rotate action only circuit means and a down-count shed circuit means for controlling said add and shed detection logic circuit means and for controlling the operating direction of said address generating means such that said second-type loads are added in the order in which their load control latch means are addressed in said predetermined sequence and are shed in the reverse of said order, and such that said first-type loads are added only after all the second-type loads that are controlled by those of said load control latches addressed by address signals that precede said consecutive address signals in said sequence have been added and are shed only after all the second-type loads that are controlled by those of said load control latches addressed by address signals that follow said consecutive address signals have been shed.

16. A method of automatically controlling the "on/off" states of each of a plurality of electrical loads in response to the steps of monitoring the level of the electrical power delivered to the "on" loads, producing an add control signal for commanding the addition of one of the plurality of loads when power consumption is to be increased, and producing a shed control signal for commanding the shedding of one of the plurality of loads when power consumption is to be decreased, comprising the steps of:

controlling the "on/off" states of each of the plurality of electrical loads by a corresponding plurality of individually addressable electrical latches, one for each load, wherein each said latch, when addressed, is capable of being disposed in either a load-off state in which the load controlled thereby is switched "off", or a load-on state in which the load controlled thereby is switched "on";

repetitively generating a predetermined sequence of latch-addressing signals and applying said signals to said latches so as to individually address said latches in a given sequence;

sensing the state of each of said latches at a time when each such latch is being addressed by a corresponding one of said latch-addressing signals;

detecting the concurrence of said add control signal and the sensing of a load-off state of one of said latches and in response thereto switching such latch to its load-on state; and

detecting the concurrence of said shed control signal and the sensing of a load-on state of one of said latches and in response thereto switching such latch to its load-off state.

17. The method of claim 16, further comprising the step of automatically changing said predetermined sequence in which said latch-addressing signals are generated to control the sequence in which the loads are switched between their "on" and "off" states in response to said add and shed control signals.

18. The method of claim 17 wherein said step of automatically changing said predetermined sequence comprises the step of selectively reversing said predetermined sequence.

19. The method of claim 17 wherein said step of automatically changing said predetermined sequence comprises the step of selectively skipping certain of said latch-addressing signals in said predetermined sequence.