Associative memory with neighboring recirculated paths offset by one bit

• US 4,065,756 A
• Filed: 03/15/1976
• Issued: 12/27/1977
• Est. Priority Date: 03/15/1976
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Panigrahi, Godavarish
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/666,575
• Time in Patent Office: 652 Days
• Field of Search: 340/173 AM, 340/173 RC
• US Class Current: 365/49.1
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers

Abstract

This disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations (loops) being searched concurrently although word access is serial in manner. Data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location, the second bit of the second word is at its comparison location and so forth. The comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops. Content addressing logic includes a series of match bit shift registers, one for each comparison location, to record match occurrences. When a word match occurs, the address of the respective word loop is sent to the memory to read out the data bits stored therein. Various embodiments are disclosed to illustrate that the memory may be formed of any number of word locations having any number of bit positions per word.

Claims

1. An associative memory comprising:

a plurality of circular dynamic memory data paths in each of which one or more series of bits representing words are serially stored such that corresponding significant bits in the respective paths are offset by one bit from corresponding bits in neighboring paths;

comparison logic;

a comparand shift register having individual bit positions being coupled by said comparison logic to individual ones of said memory data paths; and

timing means coupled to said data paths and to said comparand register to shift comparand bits in said comparand register in synchronism with the shifting of all of the data bits in said respective data paths, such that the comparand data bits will be concurrently compared with individual data bits from all of said data paths.

2. An associative memory according to claim 1 wherein said memory data paths are formed of pairs of shift registers coupled at both ends to circulate said data bits.

3. An associative memory according to claim 2 wherein said shift registers are charge coupled device shift registers.

4. An associative memory according to claim 1 which includes N memory data paths each capable of holding N data bits.

5. An associative memory according to claim 1 wherein there are 2N data paths each capable of holding N data bits.

6. An associative memory accordng to claim 1 further including:

a mask shift register coupled to said comparand shift register and to said comparison logic to provide mask bits for comparison with said data bits in said data paths and said comparand bits.

7. A content addressable memory comprising:

a plurality of circularly coupled data shift registers to store data bits to be recirculated therethrough, each of said shift register having one or more series of bits representing words which are serially stored therein such that corresponding significant bits in the respective shift registers are offset by one bit from corresponding bits in neighboring shift registers;

comparison logic;

a comparand shift register having individual bit positions being coupled by said comparison logic to individual ones of said shift registers; and

timing means coupled to said data shift registers and to said comparand shift register to shift comparand bits in said comparand register in synchronism wit the shifting of data bits in all of said respective data shift registers, such that the comparand data bits will be concurrently compared with individual data bits from all of said data shift registers.

8. A content addressable memory according to claim 7 wherein said shift registers are charge coupled device shift registers.

9. A content addressable memory according to claim 7 which includes N memory data shift registers each capable of holding N data bits.

10. A content addressable memory according to claim 7 wherein there are 2N data shift registers each capable of holding N data bits.

11. A content addressable memory according to claim 7 further including:

a mask shift register coupled to said comparand shift register and to said comparison logic to provide mask bits for comparison with said data bits in said data shift registers and said comparand bits.