Method and apparatus for synchronizing data and clock signals

• US 4,065,862 A
• Filed: 09/15/1975
• Issued: 01/03/1978
• Est. Priority Date: 09/15/1975
• Status: Expired due to Term

• Current Assignee: American Express Company
• Original Assignee: American Express Company
• Inventors: Meyer, Russell L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Bartz, C. T.
• Application Number:
  US05/613,249
• Time in Patent Office: 841 Days
• Field of Search: 340/172.5, 178/69.5, 364/200
• US Class Current: 713/400
• CPC Class Codes: G06F 13/4269 using a handshaking protocol, e.g. Centronics connection
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20

Abstract

Method and apparatus for synchronizing data signals with clock pulses in a data transmission computer system having a computer for generating data signals and a local data set for transmitting the data signals to a remotely located data set, includes a receiving register for storing the data signals and a transmitting register coupled to the output of the receiving register for receiving and storing data signals from the receiving register. Logic circuits respond to clock signals from the local data set to cause the data signals to be transferred from the receiving register to the transmitting register and from there to the local data set. The clock pulses from the local data set are synchronized with the data signals as they are stored in the receiving register, the data signals being transferred from the transmitting register to the local data set under the control of the logic circuits in synchronism with the clock signals from the local data set.

Claims

1. In a data transmission computer system having a computer for generating data signals and a local data set having means for transmitting the data signals to a remotely located data set over a transmission line which interconnects said local data set and said remotely located data set, said local data set having means for providing recurring clock pulses at a clock output thereof, an arrangement for synchronizing the data signals with the clock pulses, comprising:

a receiving register coupled to an output of said computer for receiving and storing the data signals generated by the computer, said receiving register including status means for providing a status signal whenever said receiving register is storing a given number of said data signals;

synchronizing means for providing clock signals for application to a clock input of said receiving register to enable said receiving register to store the data signals, said synchronizing means having first means coupled to said clock output of said local data set, and being responsive to the clock pulses provided by said local data set to provide first and second timing pulses related in frequency to the frequency of said clock pulses, and second means having an input connected to an output of said first means to receive said first timing pulses, and a further input coupled to said output of said computer for receiving said data signals, said second means being responsive to said first timing pulses and to said data signals to provide said clock signals whereby the data signals are synchronized with the clock pulses as the data signals are stored in said receiving register;

a transmitting register coupled to the output of said receiving register for receiving the data signals from said receiving register and for storing the data signals;

means coupling the output of said transmitting register and a data input of said local data set;

control logic means having an input connected to an output of said status means to receive said status signal and further input connected to a further output of said first means to receive said second timing pulses, said control logic means being responsive to said status signal and said second timing pulses to provide transfer signals for effecting the transfer of the data signals from the receiving register to the transmitting register; and

means for extending the clock pulses provided by said local data set to a clock input of said transmitting register to cause the data signals, which are transferred to said transmitting register under the control of said control logic means, to be transferred from said transmitting register to the local data set at a rate determined by the clock pulses provided by said local data set.

2. An arrangement according to claim 1, wherein said first means of said synchronizing means includes a phase locked loop responsive to said clock pulses for generating phase locked timing pulses at a frequency which is an integral multiple of the frequency of said clock pulses, said second means being responsive to said phase locked timing pulses and to said data signals for providing a clock signal for application to said receiving register at the midpoint in time of each data signal.

3. An arrangement according to claim 2, wherein said phase locked loop includes a voltage controlled oscillator and a reference establishing circuit for enabling said voltage controlled oscillator to generate the phase locked pulses at a rate equal to N times the rate of the clock pulses from the local data set.

4. An arrangement according to claim 3, wherein said N equals 64.

5. An arrangement according to claim 3, further including capacitance means for causing the voltage controlled oscillator to have a selected one of a plurality of different output frequencies.

6. An arrangement according to claim 5, wherein said capacitance means includes a pair of resistance-capacitance circuits and a switch for selecting one of them to couple the selected one to the oscillator.

7. An arrangement according to claim 1, wherein said receiving register includes an input shift register for receiving the data signals from the computer in serial asynchronous form, and a receiving buffer storage register having parallel inputs connected to parallel outputs of said input shift register whereby said data signals can be transferred from said input shift register to said receiving buffer storage register in a parallel mode of operation.

8. An arrangement according to claim 7, wherein said transmitting register includes a transmitting buffer storage register having parallel inputs connected to parallel outputs of said receiving buffer storage register for receiving said data signals from said receiving register and an output shift register having parallel inputs connected to parallel outputs of said transmitting buffer storage register whereby said data signals can be transferred from said transmitting buffer storage register to said output shift register in a parallel mode of operation, said data signals being shifted out of said output shift register under the control of said clock pulses for transfer to said local data set.

9. An arrangement according to claim 8 wherein said receiving register includes first transfer timing means responsive to said second means of said synchronizing means for effecting the transfer of the data signals between said input shift register to said receiving buffer storage register.

10. An arrangement according to claim 9, wherein said control logic means includes first transfer means having means responsive to said status signal for generating a data strobe signal for application to said receiving buffer storage register to cause the data signals in said receiving buffer storage register to be transferred to said parallel outputs of said buffer storage register.

11. An arrangement according to claim 10, wherein said control logic means includes second transfer means having means responsive to said data strobe signal and one of said second timing signals for generating a load strobe signal for enabling said transmitting buffer storage register to receive said data signals from said parallel outputs of said receiving buffer storage register, said load strobe signal being generated within a predetermined time following the initial generation of said data strobe signal.

12. An arrangement according to claim 11, wherein said transmitting buffer storage register provides a buffer empty signal whenever said transmitting buffer storage register is empty, said transmitting register including second transfer timing means operable when enabled to effect the transfer of the data signals between said transmitting buffer storage register and said output shift register, said control logic means further including transfer control means responsive to said buffer empty signal to enable said first transfer means to respond to said status signal, said transfer control means being operable to enable said second transfer timing means, and to disable said second transfer means for terminating said load strobe signal, and means responsive to said transfer control means and said second timing pulses to disable said first transfer means for terminating said data strobe signal within a given time following the termination of said load strobe signal.

13. An arrangement according to claim 1, wherein said control logic means includes first transfer means responsive to said status signal for generating a data strobe signal to prepare the data signals in said receiving register to be transferred to said transmitting register.

14. An arrangement according to claim 13, wherein said control logic means further includes second transfer means responsive to said first transfer means and said second timing pulses for generating a load strobe signal for enabling said transmitting register to receive said data signals from said receiving register, said load strobe signal being generated within a predetermined time following the initial generation of said data strobe signal.

15. An arrangement according to claim 14, wherein said control logic means further includes transfer control means enabled by said transmitting register in response to the transfer of data signals thereto, to disable said second transfer means for terminating said load strobe signal, and means responsive to said transfer control means and to said second timing pulses to disable said first transfer means for terminating said data strobe signal within a given time following the termination of said load strobe signal.

16. An interface circuit adapted for use in a data transmission system having a data processor for generating data signals in an asynchronous serial manner, and having a data set having means for providing clock pulses and means for sending the data signals over a transmission line to a remote location in a synchronous manner under the control of clock pulses provided by said data set, comprising:

receiving register means having a serial data input coupled to an output of said data processor means for receiving and storing the data signals from said processor, said receiving register means including status means for providing a status signal whenever said receiving register is storing a given number of said data signals;

synchronizing means having first means coupled to a clock output of said data set, and being responsive to the clock pulses provided by said data set to provide first and second timing pulses related in frequency to the frequency of said clock pulses, and second means having an input connected to an output of said first means to receive said first timing pulses, and a further input coupled to said output of said computer for receiving said data signals, said second means being responsive to the data signals and said first timing pulses for providing clock signals for application to a clock input of said receiving register means to enable it to receive said data signals in synchronism with the clock pulses;

buffer means having parallel data inputs connected to parallel data outputs of said receiving register means for temporarily receiving the synchronized data signals from said receiving register means;

control logic means including transfer means having an input connected to an output of said status means to receive said status signal and a further input connected to a further output of said first means to receive said second timing pulses, said transfer means being responsive to said status signal and said second timing pulses to provide transfer signals for application to said receiving register means and said transmitting register means for transferring the synchronized data signals to said buffer means; and

transmitting register means having parallel data inputs connected to parallel data outputs of said buffer means for receiving said synchronized data signals from said buffer means, means coupling a serial data output of said transmitting register means to a data input of said data set, and means connected between a clock output of said data set and a clock input of said transmitting register for extending the clock pulses to said transmitting register means to cause the synchronized data signals to be transferred in serial form to said data set for transmission thereby over said transmission line to said remote location.

17. An interface circuit according to claim 16, wherein said transfer means includes first transfer means responsive to said status signal for generating a data strobe signal to prepare the data signals in said receiving register to be transferred to said transmitting register.

18. An interface circuit according to claim 17, wherein said transfer means further includes second transfer means responsive to said first transfer means and said second timing pulses for generating a load strobe signal for enabling said transmitting register to receive said data signals from said receiving register, said load strobe signal being generated within a predetermined time following the initial generation of said data strobe signal.

19. An interface circuit according to claim 18, wherein said control means further includes transfer control means enabled by said transmitting register in response to the transfer of data signals thereto, to disable said second transfer means for terminating said load strobe signal, and means responsive to said transfer control means and to said second timing pulses to disable said first transfer means for terminating said data strobe signal within a given time following the termination of said load strobe signal.

20. An interface circuit adapted for use in a data transmission system having a data processor for generating asynchronous data signals and having a data transceiving means connected to a transmission line for sending the data signals over said transmission line to a remote location in a synchronous manner under the control of clock pulses provided by the data transceiving means comprising:

a receiving register having an input shift register and a receiving buffer register, said input shift register having a serial input coupled to an output of said data processor means for receiving said data signals, and having parallel outputs connected to parallel inputs of said receiving buffer register, and status means for providing a status signal whenever said receiving buffer register is storing data signals;

a transmitting register including a transmitting buffer register and an output shift register, said transmitting buffer register having parallel inputs connected to parallel outputs of said receiving buffer register, and having parallel outputs connected to parallel inputs of said output shift register, said output shift register having a serial output coupled to said data transceiving means;

synchronizing means having first means coupled to said clock output of said data transceiving means, and being responsive to said clock pulses provided by said data transceiver means to provide first and second timing pulses related in frequency to the frequency of said clock pulses, and second means having an input connected to an output of said first means to receive said first timing pulses, and a further input coupled to said output of said data processor for receiving said data signals, said second means being responsive to said first timing pulses and to said data signals to provide said clock signals for application to a clock input of said input shift register to cause said data signals to be shifted into said input shift register whereby said data signals are synchronized with the clock pulses as the data signals are shifted into said input register;

control logic having an input connected to an output of said status means to receive said status signal and a further input connected to a further output of said first means to receive said second timing pulses, said control logic being responsive to said status signal and said second timing pulses to provide transfer signals to said buffer storage registers for effecting the transfer of the data signals from said input shift register to said output shift register over the associated buffer storage registers; and

means for extending said clock pulses to a clock input of said transmitting register to cause said data signals to be serially shifted out of said output shift register for transfer to said data transceiving means for transmission thereby over said transmission line to said remote location.