System for pretesting electronic memory locations and automatically identifying faulty memory sections

• US 4,066,880 A
• Filed: 03/30/1976
• Issued: 01/03/1978
• Est. Priority Date: 03/30/1976
• Status: Expired due to Term

• Current Assignee: Tanknology/Engineered Systems, Inc.
• Original Assignee: Engineered Systems Incorporated
• Inventors: Salley, Ernest J.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/671,938
• Time in Patent Office: 644 Days
• Field of Search: 235/153 AC, 235/153 AM, 340/174 ED, 340/173 BB, 364/200, 364/900
• US Class Current: 714/6.13
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

An MOS RAM read/write memory system has thirty-two 1 × 512 bit RAM memory chips arranged in a matrix. The system pretests all data bit locations for each address prior to the entry of any data into that address, and automatically skips an address having a faulty data bit location in it. In addition, the system functions, upon reading out of data information from the memory chips, to uniquely identify any faulty MOS RAM memory chip; so that it may be removed and replaced if desired.

Claims

1. A system for detecting errors and identifying error locations in read/write memory during use of such memory, including in combination:

read/write memory means for storing a plurality of binary encoded words at a plurality of address locations, each word having at least two binary bits, said memory means initially being cleared to a condition in which all of the binary bits thereof should be of the same type;

identifying means coupled with said memory means and responsive to a readout of the words stored therein for identifying a faulty bit of a word at any address location which is not cleared; and

addressing means for selecting different address locations in said memory means, and means coupled with said identifying means for causing said addressing means to select a new address location upon identification of a faulty bit by said identifying means.

2. The combination according to claim 1 wherein said memory means is configured to store a predetermined number of words at each address location and further including scanning means coupled with said memory means for selecting word locations within said selected address location, said addressing means and said scanning means causing said word locations in said memory means to be read out in a predetermined sequence.

3. The combination according to claim 2 wherein said identifying means comprises means for displaying indicia uniquely representative of each different combination of binary bits in each of said binary encoded words.

4. The combination according to claim 3 wherein the predetermined number of words at each address location comprises a message, and said display by said identifying means of a word having all of said bits thereof of the same type causes a predetermined word to be displayed in the message of which such word is a part, the display of any such predetermined word in a message being indicative of an error condition in any other word of said message which is not said predetermined word.

5. A system for detecting errors and identifying error locations in read/write memory during use of such memory, including in combination:

read/write memory means for storing a plurality of binary encoded words at a plurality of address locations, each word having at least two binary bits, said read/write memory means comprised of K times J memory chips, each having a capacity of I bits, wherein K is the number of bits in each binary encoded word, J is the number of words in a message stored at each address location, and I is the number of different address locations, said memory chips being arranged so that corresponding bits of each of the words in each of the address locations are stored in a single memory chip, so that the first bit of the first word in each address location is stored in a first memory chip, with the last bit of the last word in each message being stored in the last (K times J) memory chip, said memory means initially being cleared to a condition in which all of the binary bits thereof should be of the same type; and

identifying means coupled with said memory means and responsive to a readout of the words stored therein for identifying a faulty bit of a word at any address location which is not cleared.

6. The combination according to claim 5 wherein said identifying means comprises printing means for printing unique symbols representative of the binary bit sequence of each of the binary encoded words, and wherein a symbol other than the symbol for a predetermined word occurring in any message also including a symbol for said predetermined word is indicative of a faulty memory bit location in the word represented by such other symbol, thereby uniquely identifying a faulty memory chip out of the total K times J memory chips used in the system.

7. The combination according to claim 6 wherein K is equal to 4, said identifying means includes means for adding three predetermined bits to each of said words read out from said memory means to encode said words in the ASCII code, and said printing means comprises a printer responsive to said ASCII code.

8. A system for testing-before-storing binary encoded data in a read/write memory including in combination:

read/write memory means having a plurality of bit locations for storing a plurality of binary encoded words at a plurality of address locations, each of said words comprised of at least two binary data bits, said memory means initially being cleared to cause all of the address locations of said memory means to store the same predetermined type of binary data bit at all bit locations of said memory means;

addressing means for selecting address locations in said memory means;

scanning means coupled with said memory means for scanning all of the word locations at the selected address;

readout means coupled with said memory means for reading out the binary encoded words stored in each address location and providing a first output for each such address location when all of the binary bits thereof are of the same predetermined type and for providing a second output when any one binary data bit of the words stored at any address location is not of said same predetermined type;

means coupled with said readout means for incrementing said addressing means to the next address location of said memory means in response to the second output of said readout means to repeat the cycle and read out the words in the next address location;

data entry means for writing uniquely encoded binary data into address locations of said memory means; and

means coupled with said readout means and responsive to the first output thereof for enabling said data entry means to write data into an address location following said readout to determine that binary bits of said predetermined type previously were stored at all bit locations of such address location.

9. The combination according to claim 8, wherein said readout means comprises coincidence gate means, and a bistable multivibrator responsive to the output of said gate means and to a predetermined output of said scanning means for advancing said addressing means in response to the second output from said coincidence gate means.