Sampled signal processing device

• US 4,066,881 A
• Filed: 08/12/1976
• Issued: 01/03/1978
• Est. Priority Date: 08/13/1975
• Status: Expired due to Term

• Current Assignee: Compagnie industrielle des télécommunications CIT-ALCATEL
• Original Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel SA
• Inventors: Houdard, Jean-Pierre
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US05/713,947
• Time in Patent Office: 509 Days
• Field of Search: 235/152, 235/156, 324/77 B
• US Class Current: 708/405
• CPC Class Codes: G06G 7/1921 for forming Fourier integrals, harmonic analysis and synthesis spectrum analysis G01R23/00

Abstract

A device for performing the discrete Fourier transform on a sequence of an arbitrary number N of equally spaced signal samples. The device includes a digital filter having a transfer function: ##EQU1## Calculation coefficients sin 2πr/N and cos 2πr/N depend on the value of N and are calculated using the same digital filter during a starting-up operation. The values of the coefficients are stored and the device is "primed" to a particular value of N. If a different number of samples N'"'"' is subsequently needed, a new priming pass sets the device up.

Claims

1. A device for performing the discrete Fourier transform on a sequence of an arbitrary number, N, of equally spaced samples x(nT) of a signal x(t) to be processed, the device including a signal sample memory for the N samples x(nT), digital filter means having a transfer function H(z) with an input receiving samples from said memory to a pair of outputs, where:

##EQU19## and ##EQU20## and r is the order of the Fourier coefficient being calculated, the digital filter being such that application of the N samples in sequence at its input causes its outputs to produce respectively the real and imaginary components of the r-th Fourier coefficient, the device further comprising a respective sine/cosine memory for storing values of a_r and b_r for different r, and the filter including multiplier means connected to respective sine/cosine memory to introduce the appropriate values of a_r and b_r into the filter during calculation, and switch means, coupled to said filter for putting the the device into a configuration in which a respective sine/cosine memory is connected to store successive values at the filter outputs for future use as values of a_r and b_r for successive r, the multiplier means connected to an input for initial values ##EQU21## and the filter input connected to receive a unit impulse function u(rT) instead of the signal samples, where u(rT) = 1 for R = o and o for r ≠

o.

2. A device according to claim 1, wherein the digital filter comprises a three-input adder having a first input constituting the filter input, a delay circuit having two stages of unit delay connected in series to the output of the three-input adder, the output of the first stage of said delay circuit being returned to a second input of the three-input adder via a multiplier having a multiplying factor switchable between 2a₁ and 2a_r and the output of the second stage being inverted and returned to the third input of the three-input adder;

the first filter output being connected to the output of a two-input adder having a first input connected to the output of the three-input adder and a second input connected to the output of the first stage of the delay circuit via a multiplier having a multiplying factor switchable between -a₁ and -a_r ;

the second output being connected to the output of the first stage of the delay means via a muliplier having a multiplying factor switchable between b₁ and b_r.