Digital bit image memory system

• US 4,069,511 A
• Filed: 06/01/1976
• Issued: 01/17/1978
• Est. Priority Date: 06/01/1976
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Lelke, Helmut
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Bartz, C. T.
• Application Number:
  US05/691,686
• Time in Patent Office: 595 Days
• Field of Search: 340/172.5, 340/324 AD, 364/200
• US Class Current: 345/545
• CPC Class Codes: B41B 27/00 Control, indicating, or safety devices or systems for composing machines of various kinds or types computers in general G06F
• CPC Class Codes: G06F 3/153 using cathode-ray tubes
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A digital bit image memory system especially adapted for use in a newspaper-type composition and display system. At least one digital storage location is provided for each elemental display position. The memory system is formed with plural rows and columns of random access memory devices which are arranged and continually addressed to simultaneously refresh the display and maintain the stored data.

Claims

1. A bit image memory for use with a visual display comprising in combination:

a semiconductor memory, said memory having at least one digital storage location for each elemental display position upon said visual display; and

means for reading out data from said memory to produce an image upon said visual display, said reading-out means being coupled to address inputs and data outputs of said memory, said memory being refreshed within the refresh time period of said visual display means.

2. The combination of claim 1 wherein:

said semiconductor memory comprises a plurality of semiconductor random access memories.

3. The combination of claim 2 wherein:

each of said random access memories has a plurality of address input lines, predetermined ones of said address input lines being activated within a predetermined maximum refresh time determined to insure data retention with each of said random access memories.

4. The combination of claim 3 further comprising:

means for reading out data from said semiconductor memory to produce a video signal for operating said visual display means.

5. The combination of claim 4 wherein said reading out means comprises:

a plurality of shift registers.

6. The combination of claim 5 wherein:

outputs for each of said shift registers are combined to form said video signal.

7. A bit image memory system for refreshng one or more raster scanned visual display devices comprising in combination:

a plurality of random access memory devices, said devices being arranged in a plurality of rows and columns;

a first plurality of shift registers, one or more inputs of each shift register of said first plurality of shift registers being coupled to data outputs of said random access memory devices for receiving data read out from one of said columns of memory devices;

a second plurality of shift registers, one or more inputs of each shift register of said second plurality of shift registers being coupled to outputs of at least two of said first plurality of shift registers for receiving data from said first plurality of shift registers;

means for shifting data out of said shift registers of said second plurality of shift registers one of said shift registers of said second plurality of shift registers at a time; and

means for summing the outputs of said shift registers of said second plurality of shift registers.

8. The combination of claim 7 wherein said random access memory devices each comprise:

an MOS random access memory chip.

9. The combination of claim 7 wherein:

each of said random access memory devices has a plurality of address input lines, predetermined ones of said address input lines requiring activation within a predetermined maximum time period to retain data stored in said memory devices.

10. The combination of claim 9 further comprising:

means for producing digital signals for addressing said random access memory devices, said digital signals being coupled to address inputs of said random access memory devices.

11. The combination of claim 10 wherein:

said digital signals for addressing said random access memory represents positions upon the display surface of one of said visual display devices.

12. The combination of claim 11 wherein:

said digital signals representing said positions are ordered in a binary sequence;

said address input lines are ordered in a binary sequence; and

at least some of said digital signals representing said positions are coupled to said address input lines in other than corresponding order.

13. A digital data display system comprising in combination:

means for producing digital signals representing character patterns;

means for producing digital signals representing line patterns;

a plurality of display means;

a plurality of memory modules for storing data in response to said digital signals representing said character and line patterns, two of said memory modules being provided for storing said character and line patterns for each of said display means;

means for reading data out of said memory modules, said reading-out means being coupled to data outputs of said memory modules; and

means for converting the read-out data from said memory modules to a video signal for operating said display means.

14. The combination of claim 13 wherein said display means each comprises:

raster scanned cathode-ray tube display means.

15. The combination of claim 14 wherein:

each raster scan line upon each of said display means is divided into a plurality of segments, data for producing said video signal for adjacent ones of said line segments being coupled from alternate ones of said memory modules; and

said reading-out means comprises means for alternately reading data out of two of said memory modules.

16. The combination of claim 15 wherein each of said memory modules comprises:

a plurality of rows and columns of random access memory devices, each of said memory devices having a plurality of address input lines, at least one data input line, and at least one data output line, corresponding ones of said address input lines from each of said memory devices being coupled together and said data output lines from said memory devices within each column being coupled to one of a plurality of shift registers, one of said columns of memory devices being provided for each elemetal display area within each of said segments.

17. The combination of claim 16 further comprising:

means for addressing said memory devices, said addressing means producing addressing signals coupled to address inputs of said memory devices.

18. The combination of claim 17 wherein said memory devices each comprise:

a 1 ×

N-bit MOS random access memory.

19. The combination of claim 18 wherein:

said addressing means activates predetermined ones of said address input lines within a predetermined maximum time period during normal refresh of said display means to maintain said data stored in said memory devices.