Semiconductor component with dielectric carrier and its manufacture

• US 4,070,230 A
• Filed: 06/04/1976
• Issued: 01/24/1978
• Est. Priority Date: 07/04/1974
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Stein, Karl-Ulrich
• Primary Examiner(s): Powell, William A.
• Application Number:
  US05/692,664
• Time in Patent Office: 599 Days
• Field of Search: 156/3, 156/8, 156/11, 156/17, 156/654-657, 156/659, 156/662, 156/648, 156/649, 96/36.2, 96/38.4, 29/580, 29/588, 29/589, 29/590, 148/187, 427/89, 427/90, 427/82, 427/85, 427/88, 357/55
• US Class Current: 438/411
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02348 treatment by exposure to UV light
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A semiconductor component of a semiconductor or circuit system is provided. The circuit incorporates a dielectric carrier comprised of synthetic material. The circuit is provided with plate-shaped semiconductor islands. The islands possess doping layers and are interconnected as desired with a thin film wiring. A process for the production of such product is also provided.

Claims

1. A process for the production of a component assembly incorporating a flattened, integrated semiconductor circuit of the type having a plurality of discrete sites of doped, semiconductor material which discrete sites are interconnected together in a predetermined manner by layered paths of conductive material, said process comprising the steps of:

A. forming a said semiconductor circuit on an n⁺ conducting silicon wafer by depositing an n^- conductive monocrystalline epitaxial silicon layer thereon, diffusing p-conducting doping material into said epitaxial layer selectively to form doped zones, depositing an insulative layer selectively thereover, and depositing electrically conductive paths selectively thereover,

B. forming a layer of polyamide resin over the resulting said semiconductor circuit,

C. heating said layer of polyamide resin to convert same into a layer of polyimide resin,

D. selectively etching away portions of said n⁺ silicon wafer and said n^- epitaxial silicon layer.

2. The process of claim 1 wherein, following said etching away, only plate-shaped doped islands of said n^- epitaxial silicon layer remain.

3. The process of claim 1 wherein said polyamide resin layer is applied in the form of a photo-lacquer layer.

4. The process of claim 1 wherein said portions of said n⁺ silicon wafer so selectively etched away lie over said resulting semiconductor circuit whereby a frame of said n⁺ silicon wafer remains perimetrically about peripheral edge portions of said resulting semiconductor circuit, said frame serving as a support for said layer of polyamide resin.

5. The process of claim 4 wherein soldering bumps are applied through said layer of polyamide resin over the region of said frame.

6. The process of claim 5 wherein a plurality of said circuits are simultaneously so produced by said steps, said plurality being arranged in spaced, parallel laterally adjacent rows upon said silicon wafer, said frame of each said resulting semiconductor circuit being interconnected to each laterally adjacent said resulting semiconductor circuit by thin arms comprised of said silicon wafer, said arms being adapted for transverse slitting.

7. The process of claim 6 wherein following said etching, the resulting surface is passivated by ion implantation.

8. The process of claim 6 wherein following said etching the resulting surface is passivated by coating with a layer of synthetic resin.