Phase comparison systems employing improved phaselock loop apparatus

• US 4,070,634 A
• Filed: 10/02/1975
• Issued: 01/24/1978
• Est. Priority Date: 06/17/1974
• Status: Expired due to Term

• Current Assignee: Sp-Marine Incorporated (Northrop Grumman Corporation)
• Original Assignee: Navidyne Corporation
• Inventors: Barker, A. Clifford, Zavada, Edmund S.
• Primary Examiner(s): Kominski, John
• Application Number:
  US05/618,778
• Time in Patent Office: 845 Days
• Field of Search: 331/2, 331/10, 331/18, 331/17, 331/64
• US Class Current: 331/2
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation

Abstract

A high-accuracy phase comparison system for noise-contaminated fixed-frequency input signals, such as Omega radionavigation signals, employs a pair of phaselock loops in which output pulses from a high-frequency oscillator are deleted at the frequency of a variable-frequency oscillator which is responsive to the detected phase difference between the associated input signal and an associated reference signal, thereby to provide a high-frequency intermediate signal which is frequency-divided to produce the reference signal continuously and free of noise. The relative phase of the input signals may be determined by phase-comparing the reference signals of the two phaselock loops or, to provide even higher precision, by phase-comparing the variable-frequency signals of the two loops.

Claims

1. A phase comparison system comprising a pair of phase lock loops responsive to first and second input signals, respectively, and means for comparing corresponding output signals of said phase lock loops, each phase lock loop comprising:

means for producing an error signal representative of the phase difference between an input signal and a reference signal;

means responsive to said error signal for generating a signal having a frequency which varies in accordance with said phase difference;

means for generating a pulse train signal having a pulse repetition frequency which is orders of magnitude higher than the frequency of said variable-frequency signal; and

means for deriving said reference signal from said variable-frequency signal and said pulse train signal, said deriving means including a pulse deletion circuit which deletes pulses from said pulse train signal in response to said variable-frequency signal.

2. A system as set forth in claim 1, wherein the pulse train signals for both phaselock loops are provided by the same oscillator.

3. A system as set forth in claim 1, wherein said means for comparing corresponding output signals comprises means for comparing the phases of the reference signals of the two phaselock loops.

4. A system as set forth in claim 1, wherein the frequency of said pulse train signals is substantially fixed.

5. A system as set forth in claim 1, wherein said means for comparing corresponding output signals comprises means for comparing the phases of the variable-frequency signals of the two phaselock loops.

6. A system as set forth in claim 1, wherein, in each phaselock loop, the deletion of pulses from the pulse train signal produces an intermediate signal having a frequency different from the frequency of the input signal and the deriving means includes means for changing the frequency of the intermediate signal to produce the reference signal.

7. A system as set forth in claim 6, wherein, in each phaselock loop, the intermediate signal has a frequency which is an integral multiple of the frequency of the input signal, and the frequency-changing means comprises a frequency divider.

8. A system as set forth in claim 6, wherein, in each phaselock loop, the means for generating the pulse train signal comprises a stable oscillator.

9. A system as set forth in claim 6, wherein, in each phaselock loop, the frequency of the pulse train signal is substantially equal to an integral multiple of the frequency of the input signal plus the nominal frequency of the variable-frequency signal, the intermediate signal has a frequency which is substantially equal to the integral multiple of the frequency of the input signal, and the frequency-changing means comprises means for dividing the frequency of the intermediate signal to provide the reference signal with a frequency equal to that of the input signal.

10. A system as set forth in claim 6, wherein each input signal comprises a 10.2 kHz Omega radionavigation signal.

11. A system as set forth in claim 1, wherein, in each phaselock loop, the deriving means includes means for imparting a cyclic phase dither to the reference signal.

12. A system as set forth in claim 1, wherein, in each phaselock loop, the means for generating the variable-frequency signal comprises a voltage-controlled oscillator, and wherein each phaselock loop further comprises means for integrating the error signal to provide the control signal for the oscillator.

13. A system as set forth in claim 1, wherein, in each phaselock loop, the frequency of the variable-frequency signal is orders of magnitude below the frequency of the input signal.

14. A system as set forth in claim 1, wherein said phase-comparing means comprises means for detecting relative phase shifts of a predetermined amount between the variable-frequency signals and means for counting the number of such phase shifts.

15. A system as set forth in claim 14, wherein said counting means comprises an up/down counter, and wherein said detecting means comprises means for initiating an "up" count when said relative phase shift is in a first direction and for initiating a "down" count when said relative phase shift is in the opposite direction.

16. A system as set forth in claim 14, wherein said predetermined amount is substantially 2π

radians.

17. A system as set forth in claim 14, wherein said phase-comparing means further comprises means for measuring phase differences which are less than said predetermined amount.