Parallel requestor priority determination and requestor address matching in a cache memory system

• US 4,070,706 A
• Filed: 09/20/1976
• Issued: 01/24/1978
• Est. Priority Date: 09/20/1976
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation
• Original Assignee: Sperry Rand Corporation
• Inventors: Scheuneman, James Herman
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Bartz, C. T.
• Application Number:
  US05/724,681
• Time in Patent Office: 491 Days
• Field of Search: 364/200
• US Class Current: 711/119
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36

Abstract

A method of and an apparatus for performing, in a Cache memory system, the Priority determination of what Requestor, of R Requestors, is to be granted priority by the Priority Network while simultaneously comparing, in parallel, all of the R Requestors'"'"' addresses for a Match condition in R Cache memories. The Cache memory system incorporates a separate Cache memory or associative memory for each Requestor, each of which Cache memories is comprised of an Address Buffer or Search memory, in which the associated Requestors'"'"' addresses are stored, and a Data Buffer or Associated memory, in which the data that are associated with each of the Requestors'"'"' addresses are stored. Thus, while the Priority Request signals from all of the requesting Requestors are being coupled to the single Priority Network, each of the requesting Requestors'"'"' addresses is coupled to each of the requesting Requestor separately associated Cache memory. As the Priority determination by the Priority Network and the Match determination by the Cache memories require approximately the same time to complete, the parallel operation thereof substantially reduces memory access time to either the Main memory or the Cache memory.

Claims

1. In an electronic data processing system, including a plurality of requestors that seek access to data stored in a like plurality of cache memories, the combination comprising:

R cache memories, each comprising;

a buffer memory having a plurality of address memory locations and a like plurality of associated data memory locations for storing a requestor address in each of said address memory locations and associated data in the associated data memory location; and

,

match determining means coupled to said address memory locations;

R requestors having a priority range, each generating an associated requesting requestor address and an associated priority request signal;

priority determining means;

means separately coupling each of said priority request signals from each separate one of said R requestors to said priority determining means for determining which one of the priority request signals generated by the requesting requestors is to be granted priority over the other ones of said requesting requestors and generating a requestor active signal indicative of the one requesting requestor that is to be granted priority;

R gating means;

means coupling each of said gating means to only a separate associated one of said R cache memories for receiving the data that are read out of the associated cache memory;

means coupling said requestor active signal from said priority determining means to only the separate associated one of said R gating means for enabling the data that were read out of the associated one of said R cache memories to be coupled to the requesting requestor that was granted priority by said priority determining means;

means coupling the requesting requestor address from each of said R requestors to only an associated separate one of said R cache memories; and

,

timing means simultaneously coupling said priority request signals to said priority determining means and each of said requesting requestor addresses to the associated cache memory for simultaneously initiating said priority determination and said match determination.

2. In an electronic data processing system including R requestors, each of which seeks access to data stored in a separate associated one of R cache memories, the combination comprising:

R cache memories, each comprising;

a buffer memory having a plurality of addressable requestor address locations and a like plurality of associated data locations for storing a requestor address in each of said addressable requestor address locations and associated data in the associated one of said data locations; and

,

match determining means coupled to said addressable requestor address locations;

R requestors having a priority range, each generating an associated requesting requestor address and an associated priority request signal;

priority determining means;

R read data registers;

means coupling each of said R read data registers to only a separate associated one of said R cache memories for receiving the data read out of the associated data locations;

means including R requestor address register means separately coupling each of said requesting requestor addresses from each separate one of said R requestors to only an associated one of said R cache memories for comparing a requesting requestor address with the requestor addresses that are stored in the addressable requestor address locations thereof and if said requesting requestor address matches one of the requestor addresses that are stored in said addressable requestor address locations gating out the associated data that are stored in the data location that is associated with the requestor address that is stored in the associated one of said addressable requestor address locations and that matched said requesting requestor address;

means separately coupling each of said priority request signals from each separate one of said R requestors to said priority determining means for determining which one of the priority request signals generated by the requesting requestors of said R requestors is to be granted priority over the other ones of said requesting requestors and generating a requestor active signal indicative of the one requesting requestor that is to be granted priority;

means coupling said requestor active signal from said priority determining means to only the separate associated one of said R read data registers for enabling the data that are read out of the associated one of said R cache memories to be coupled to only the separate associated one of said R read data registers;

timing means for generating a clocking signal; and

,

means coupling said timing means clocking signal to said priority determining means and to said R requestor address register means for simultaneously initiating said priority determination by said priority determining means and said match determination by said match determining means in all of said R cache memories.

3. In an electronic data processing system including R requestors, each of which seeks access to data stored in a separate associated one of R cache memories, the combination comprising:

R requestors having a priority range, each generating an associated requesting requestor address and an associated priority request signal;

R cache memories comprising,

an address buffer having a plurality of address locations for storing a like plurality of requestor addresses;

a data buffer having a plurality of data locations, each one of which is associated with only an associated one of said plurality of address locations in said address buffer, for storing data that are associated with the requestor address that is stored in said associated address location;

match determining means for comparing a requesting requestor address with the requestor addresses that are stored in said address locations in said address buffer and generating a Match signal if said requesting requestor address matches one of the requestor addresses that are stored in said address locations; and

,

means responsively coupled to said Match signal for reading out the data that are stored in the data location that is associated with the address location in which is stored the requestor address that matches said requesting requestor address;

means coupling the requesting requestor address from each of said R requestors to only the associated one of said R cache memories;

priority determining means;

means coupling the priority request signal from each of said R requestors to said priority determining means for determining which one of the priority request signals generated by the requesting requestors of said R requestors is to be granted priority over the other ones of said requesting requestors and generating a priority active signal that is indicative thereof;

timing means for simultaneously initiating said priority determination by said priority determining means and said match determination by each of said match determining means in each of said R cache memories;

R data gating means;

means coupling each of said R data gating means to only a separate associated one of said R cache memories for coupling the data that are read out of the associated one of said R cache memories to the separate associated one of said R data gating means;

means coupling each of said R data gating means to only the separate associated one of said R requestors; and

,

means coupling said requestor active signal from said priority determining means to only the separate associated one of said R gating means for gating the data that are read out of the associated one of said R cache memories to the separate associated one of said R requestors.