Driver circuit for driving electrochromic display device

• US 4,074,256 A
• Filed: 08/18/1976
• Issued: 02/14/1978
• Est. Priority Date: 08/20/1975
• Status: Expired due to Term

• Current Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Original Assignee: Citizen Watch Co Limited (Citizen Electronics Company Limited)
• Inventors: Sekiya, Fukuo, Ebihara, Heihachiro
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US05/715,523
• Time in Patent Office: 545 Days
• Field of Search: 340/324 R, 340/336, 350/160 R, 350/160 P, 350/160 LC, 58/152 R, 58/50 R, 58/57
• US Class Current: 345/49
• CPC Class Codes: G09G 3/16 by control of light from an independent source

Abstract

A driver circuit for driving an electrochromic display device having switching elements connected between a power source and the electrodes of the electrochromic display device. The driver circuit includes a data controller which converts a display information signal to a signal indicating a state of non-display in response to a display erase signal applied to a control terminal. A drive signal generator is responsive to the signal from the data controller to produce a bleaching signal by which a display of the electrochromic display device is erased.

Claims

1. In an electrochromic display device includng a common electrode and a plurality of segment electrodes, a driver circuit having a power source and connected to a decoder adapted to provide display information signals, comprising:

a drive signal generator for generating coloring and bleaching signals in response to first and second changes in state of each of said display information signals;

a switching device composed of complementary MOSFETs connected between power source and said segment electrodes and responsive to said coloring and bleaching signals to cause an electric current from said power source to flow through said segment electrodes in directions to induce colored and bleached states, respectively;

means for applying a display erase signal; and

data control circuit coupled between said decoder and said drive signal generator to normally pass said display information signals to said drive signal generator, said data control circuit being responsive to said display erase signal to block said display information signals being applied to said drive signal generator, whereby said drive signal generator simultaneously generates a plurality of bleaching signals to cause said complementary MOSFETs of said switching device to apply an electric current from said power source simultaneously to all of said segment electrodes which have previously been in a colored state in a direction to induce bleached state for thereby automatically erasing displaying data.

2. A driver circuit as claimed in claim 1, in which said data control circuit comprises a plurality of gate means each of which has one input coupled to an output of said decoder and the other input coupled to an output of said applying means.

3. A driver circuit as claimed in claim 1, in which said complementary MOSFETs comprise a P-channel metal oxide semi-conductor field-effect transistor having its source terminal coupled to the high potential side of said power source and its gate terminal coupled to said drive signal generator to receive said bleaching signal, and an N-channel metal oxide semi-conductor field-effect transistor having its source terminal coupled to the low potential side of said power source and its gate terminal coupled to said drive signal generator to receive said coloring signal, drain terminals of said transistors being connected to one of said segment electrodes of said electrochromic display device.

4. A driver circuit as claimed in claim 1, in which said applying means comprises a switch which is normally connected to one potential side of said power source and generates an output signal when said switch is connected to another potential side of said power source, and a synchronizing circuit coupled to said switch for synchronizing said output signal with a clock signal to generate said display erase signal in synchronism with said clock signal.

5. A driver circuit as claimed in claim 4, in which said drive signal generator comprises a plurality of latch circuits for storing said display information signals and each generating first and second output signals delayed in phase from each of said display information signals, first gate means responsive to said second output signal and said each of said display information signals to generate said coloring signal, and second gate means responsive to said first output signal and said each of said display information signal to generate said bleaching signal.

6. A driver circuit as claimed in claim 1, further comprising a change-of-state detector coupled between said data control circuit and said drive signal generator and detecting a change in state of an output of said data control circuit for thereby generating a first output signal in response to a first change in state of said output of said data control circuit and a second output signal in response to a second change in state of said output of said data control circuit, said drive signal generator being responsive to said first and second output signals to generate said coloring and bleaching signals, respectively.

7. A driver circuit as claimed in claim 6, in which said drive signal generator comprises first gate means responsive to said first output signal to generate said coloring signal, and second gate means responsive to said second output signal to generate said bleaching signal.

8. A driver circuit as claimed in claim 7, in which said first gate means comprises an AND gate having its one input coupled to said change-of-state detector to receive said first output signal and the other input coupled to said applying means, and said second gate means comprises a NOR gate having its one input coupled to said change-of-state detector to receive said second output signal and the other input coupled through an inverter to said applying means.

9. A driver circuit as claimed in claim 7, in which said first gate means comprises an AND gate having its one input coupled to said change-of-state detector to receive said first output signal and the other input coupled to said applying means, and said second gate means comprises NAND gate having its one input coupled to said change-of-state detector to receive said second output signal and the other input coupled to said applying means, and further comprising additional switching means coupled between said electrochromic display device and a ground, said additional switching means being conductive in response to said display erase signal to cause the electrodes of said electrochromic display device to be short-circuited to erase a display therefrom.

10. A driver circuit as claimed in claim 1, in which said applying means comprises a power source installation detector which generates a detection signal as said display erase signal when said power source is installed.

11. In an electrochromic display device for an electronic timepiece including a logic circuit adapted to provide logic information signals, and a decoder coupled to said logic circuit to provide display information signals in response to said logic information signals, said electrochromic display device including a common electrode and a plurality of segment electrodes, a driver circuit comprising:

a drive signal generator coupled to said decoder for generating coloring and bleaching signals in response to first and second changes in state of each of said display information signals;

a switching device composed of complementary MOSFETs connected between a power source and said segment electrodes and responsive to said coloring and bleaching signals to cause an electric current from said power source to flow through said segment electrodes in directions to induce colored and bleached states, respectively;

a control terminal for inputting a display erase signal therefrom; and

data control circuit coupled between said decoder and said drive signal generator to normally pass said display information signals to said drive signal generator, said data control circuit being responsive to said display erase signal to block said display information signals being applied to said drive signal generator, whereby said drive signal generator simultaneously generates a plurality of bleaching signals to cause said complementary MOSFETs of said switching device to apply an electric current from said power source simultaneously to all of said segment electrodes which have previously been in a colored state in a direction to induce bleached state for thereby automatically erasing a display from said display device.

12. A driver circuit as claimed in claim 11, further comprising a differentiating circuit coupled to said control terminal for generating an output signal which momentarily attains an active state for a short period of time in synchronism with said display erase signal.

13. A driver circuit as claimed in claim 12, in which said output signal generated by said differentiating circuit is applied to said drive signal generator, whereby said drive signal generator generates said bleaching signal for a short period of time.

14. A driver circuit as claimed in claim 12, in which said differentiating circuit comprises a first data-type flip-flop coupled to said control terminal, and a second data-type flip-flop coupled to an output of said first data-type flip-flop to generate said output signal delayed in phase from said display erase signal.

15. A driver circuit as claimed in claim 14, in which differentiating circuit further comprises a third data-type flip-flop coupled to an output of said second data-type flip-flop to provide an additional output signal on its output.

16. A driver circuit as claimed in claim 15, in which said switching device is responsive to said output signal from said second data-type flip-flop to cause the electrodes of said electrochromic display device to be short-circuited, and in which said drive signal generator is responsive to said additional output signal from said third data-type flip-flop to generate said bleaching signal after said electrodes have been short-circuited.

17. A driver circuit as claimed in claim 11, further comprising a power source installation detector coupled to said control terminal, said detector including means for generating a detection signal when said power source is installed, said detection signal is applied through said control terminal as said display erase signal.

18. In an electrochromic display device for an electronic timepiece including a logic circuit adapted to provide logic information signals, and a decoder coupled to said logic circuit to provide display information signals in response to said logic information signals, said electrochromic display device including a common electrode and a plurality of segment electrodes, a driver circuit comprising:

a drive signal generator coupled to said decoder for generating coloring and bleaching signals in response to first and second changes in state of each of said display information signals;

a switching device composed of complementary MOSFETs connected between a power source and said segment electrodes and responsive to said coloring and bleaching signals to cause an electric current from said power source to flow through said segment electrodes in directions to induce colored and bleached states, respectively;

a control terminal for inputting a display erase signal therefrom;

a power source installation detector coupled to said control terminal and including detection means for generating said display erase signal when said power source is installed into said electronic timepiece; and

data control circuit coupled between said decoder and said drive signal generator to normally pass said display information signals to said drive signal generator, said data control circuit being responsive to said display erase signal to block said display information signals being applied to said drive signal generator, whereby said drive signal generator simultaneously generates a plurality of bleaching signals to cause said complementary MOSFETs of said switching device to apply an electric current from said power source simultaneously to all of said segment electrodes in a direction to induce bleached state for thereby automatically erasing a display from said display device when said power source is installed into said electronic timepiece.

19. A driver circuit as claimed in claim 18, further comprising a differentiating circuit coupled to said control terminal for generating an output signal which momentarily attains an active state for a short period of time in synchronism with said display erase signal.

20. A driver circuit as claimed in claim 18, in which said power source installation detector comprises a resistor and a capacitor connected in series across the power source to form an integrating circuit, and an inverter having its input coupled to an output of said integrating circuit and an output coupled to said control terminal.

21. A driver circuit as claimed in claim 18, in which said control terminal is coupled through a resistor to one potential side of said power source, and further comprising an external control member which is normally open, said external control member being connectable to another potential side of said power source to provide said display erase signal when said power source is installed.