Inverter circuit control circuit for precluding simultaneous conduction of thyristors
First Claim
1. In a circuit for supplying an alternating current to a load which includes two power supply terminals and first and second gate-controlled thyristor switches, each said switch having a gate electrode, a main conduction path and an associated turn-off time, the main conduction paths of said switches being connected in series between said terminals with each path having a commutating diode in inverse-parallel connection therewith, an improved control network for applying complementary signals to the gate electrodes of said switches to preclude their simultaneous conduction, said control network comprising:
- means in series with said load for sensing the current through said load;
means responsive to said current sensing means for producing a trigger pulse at each zero crossing of said current;
means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn off time of said switches;
first means responsive to the cessation of each alternate one of said delay signals for producing a first signal at the gate electrode of said first switch to render it conductive; and
second means responsive to the cessation of each of the remaining alternate delay signals for producing a second signal at the gate electrode of said second switch to render it conductive.
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Accused Products
Abstract
A circuit suitable for use in an induction range. The circuit includes a resonant inverter having first and second gate controlled thyristor switches, the main conduction paths of which are serially connected between the power supply terminals. Trigger pulses for the switches are derived from the current supplied to the inverter load coil. The pulses are timed to prevent the first switch from being closed before the second switch has opened so that both switches can never be conductive at the same time. It also includes circuitry for stopping inverter operation in the event of an overcurrent condition and circuitry for adjusting the inverter output power.
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Citations
25 Claims
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1. In a circuit for supplying an alternating current to a load which includes two power supply terminals and first and second gate-controlled thyristor switches, each said switch having a gate electrode, a main conduction path and an associated turn-off time, the main conduction paths of said switches being connected in series between said terminals with each path having a commutating diode in inverse-parallel connection therewith, an improved control network for applying complementary signals to the gate electrodes of said switches to preclude their simultaneous conduction, said control network comprising:
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means in series with said load for sensing the current through said load; means responsive to said current sensing means for producing a trigger pulse at each zero crossing of said current; means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn off time of said switches; first means responsive to the cessation of each alternate one of said delay signals for producing a first signal at the gate electrode of said first switch to render it conductive; and second means responsive to the cessation of each of the remaining alternate delay signals for producing a second signal at the gate electrode of said second switch to render it conductive. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A resonant inverter circuit for converting a dc or rectified low frequency ac voltage to a relatively high frequency voltage comprising, in combination:
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first and second power supply terminals; first and second control voltage responsive switches, each switch having a control electrode and a main conduction path that passes current more readily in one direction than in the other and an associated turn off time, said switches having their main conduction paths serially connected between said first and second terminals; first and second capacitors serially connected between said first and second terminals; an induction coil connected between the common connection of said first and second switches and the common connection of said first and second capacitors forming a resonant circuit thereby; first and second nonlinear devices, said devices passing current more readily in one direction than in the other, said first and second devices being connected in inverse-parallel with the main conductive paths of said first and second switches, respectively; means for continuously sensing the flow of current through said coil to produce a trigger pulse each time said current reduces to zero; means responsive to each trigger pulse for producing a delay signal having a duration at least as great as the turn-off time of said switches; and means responsive to the cessation of each said delay signal for producing alternate signals at the gate electrodes of said first and second switches, respectively, to render each said switch separately conductive after an interval equal to the duration of said delay signal from the time current through said coil reduces to zero. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. In a circuit of the type wherein AC voltage is impressed across a load from a DC source through a switching network which includes series-connected thyristors, each having a commutating diode in inverse-parallel conduction with its principal conduction path, and a resonant circuit having capacitance and inductance disposed therein, an improved control network for applying complementary signals to the gates of the thyristors to preclude their simultaneous conduction, said control network including:
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means for generating a square wave upon the occurance of each zero current crossing through the load, the duration of said square wave being at least equal to the maximum turn off time of the thyristors; and means for alternating complementary output signals in response to the trailing edge of sequential signals from said square wave generating means, said complementary output signals being separately applied to the thyristor gates. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification