Stacked transistor output amplifier

• US 4,079,336 A
• Filed: 12/22/1976
• Issued: 03/14/1978
• Est. Priority Date: 12/22/1976
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Gross, William Harlos
• Primary Examiner(s): Dahl, Lawrence J.
• Application Number:
  US05/753,025
• Time in Patent Office: 447 Days
• Field of Search: 330/17, 330/18, 330/22, 330/38 M
• US Class Current: 330/296
• CPC Class Codes: H03F 3/42 Amplifiers with two or more amplifying elements having their dc paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
• CPC Class Codes: H03F 3/50 Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower

Abstract

In transistor output stages, where the applied voltage exceeds the voltage rating of available transistors, stacking is employed to divide the voltage across two or more series connected devices. A complementary emitter follower transistor is employed in the biasing of the stacking transistor along with a current source acting as the emitter follower load. This arrangement provides constant current drive for the stacking transistor without resorting to low value biasing resistors which produce excessive current flow under quiescent conditions.

Claims

1. A stacked transistor amplifier circuit comprising:

a signal input transistor;

a stacking transistor of the same conductivity type as said signal input transistor and having its emitter collector circuit coupled in series with the emitter collector circuit of said signal input transistor, said series transistor combination being coupled to terminals adapted for connection to a power supply;

first and second bias resistors coupled together in series combination, said series resistor combination being coupled between said terminal coupled to said collector of said stacking transistor and the base of said input transistor;

an emitter follower transistor of a conductivity type complementary to that of said signal input and said stacking transistors, the emitter of said emitter follower transistor being coupled to the base of said stacking transistor, the collector of said emitter follower transistor being coupled to the power supply terminal coupled to the emitter of said signal input transistor, and the base of said emitter follower transistor being coupled to the juncture of said resistors; and

a constant current source coupled between the power supply terminal coupled to the collector of said stacking transistor and said emitter of said emitter follower transistor.

2. The circuit of claim 1 wherein a load element is coupled in series with said collector of said stacking transistor and an output is taken from said collector.

3. A stacked transistor amplifier circuit comprising:

a signal input transistor;

a stacking transistor of the same conductivity type as said signal input transistor and having its emitter collector circuit coupled in series with the emitter collector circuit of said signal input transistor, said series transistor combination being coupled to terminals adapted for connection to a power supply;

first and second bias resistors coupled together in series combination, said series resistor combination being coupled between said terminal coupled to the collector of said stacking transistor and the emitter of said signal input transistor;

an emitter follower transistor of a conductivity type complementary to that of said signal input and said stacking transistors, the emitter of said emitter follower transistor being coupled to the base of said stacking transistor, the collector of said emitter follower transistor being coupled to the power supply terminal coupled to the emitter of said signal input transistor, and the base of said emitter follower transistor being coupled to the juncture of said resistors; and

a constant current source coupled between the power supply terminal coupled to the collector of said stacking transistor and said emitter of said emitter following transistor.

4. The circuit of claim 3 wherein a load element is coupled in series with said emitter of said signal input transistor and an output is taken from said emitter.

5. The circuit of claim 3 wherein a load element is coupled in series with said collector of said stacking transistor, input signal means coupled to said emitter of said signal input transistor , and said base of said signal input transistor is coupled to a source of reference potential.

6. A monolithic integrated circuit amplifier structure comprising in combination:

first and second NPN transistors having their emitter collector circuits coupled in series, said series coupled NPN transistors coupled between a signal output terminal and a terminal adapted for connection to the positive terminal of an operating power supply;

a first PNP transistor having the collector coupled to a terminal adapted for connection the negative terminal of said power supply, the emitter coupled to said output terminal, and the base coupled to a signal input terminal;

a second PNP transistor having the collector coupled to said terminal adapted for connection to said negative power supply terminal, the emitter coupled to the base of said first NPN transistor, and the base coupled to biasing means operative to maintain the voltage at said emitter of said second PNP transistor approximately midway between the potentials at said output terminal and said positive power supply terminal;

a current source coupled between said emitter of said second PNP transistor and said positive power supply terminal; and

means for biasing the base electrode of said second NPN transistor relative to the base electrode of said first PNP transistor to establish the operating conditions of said amplifier.

7. The structure of claim 6 wherein said PNP transistors are vertical substrate collector devices and said NPN transistors are vertical isolated collector devices.

8. The structure of claim 6 wherein each recited transistor is replaced by its complement and said power supply polarities are reversed.

9. The structure of claim 6 wherein said means for biasing comprise:

a pair of resistor elements coupled in series between said base of said second NPN transistor and said positive terminal of said power supply, the juncture of said resistors being coupled to said base of said first NPN transistor.

10. The structure of claim 6 wherein said means for biasing comprise:

a pair of resistors coupled in series between said emitter of said second NPN transistor and said positive terminal of said power supply, the juncture of said resistors being coupled to said base of said first NPN transistor.