Balancing the utilization of I/O system processors
First Claim
1. An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of program processes, said system including a plurality of modules, said modules including at least one memory module and at least a pair of individual input/output processor modules, a host processor module operative to generate signals for specifying initiation of an input/output operation assigned a particular priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:
- a pair of interrupt processing circuit means, one connected to a different one of said pair of input/output processor modules for processing interrupt requests received by the processor module on a priority basis;
processor intercommunication network means connected to each of said pair of interrupt processing logic circuits for enabling communication between said pair of processor modules;
each of said pair of processor modules comprising;
a process control register means for controlling the execution sequence of said program processes, said process control register including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at a predetermined one of a number of different priority levels; and
,control means coupled to receive interrupt request signals from said interrupt logic circuits of said system interface unit associated therewith;
said memory module including a plurality of storage locations, a group of said storage locations defining a queue for storing entries designating new processes to be initiated;
the interrupt processing circuits of one of said input/output processor modules in response to said signals being operative to apply interrupt request signals to said one processor module, said control means being operative to generate a sequence of signals for switching one of said interrupt bit positions to a predetermined state indicating the presence of an interrupt at said assigned particular priority level, and for storing an entry in said queue of said memory module, andsaid processor intercommunication means being conditioned by signals of said sequence of signals to apply a high priority type interrupt request signal to the interrupt processing circuits of said other processor module, said circuits conditioning said control means of the other processor module to generate signals for switching one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt at said priority level for enabling the less busy processor module of said pair to initiate said input/output operation.
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Abstract
An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.
The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation. The processing unit in control stores information in the memory unit to specify the interrupt priority level of the connect operation, sets an interrupt request at that same priority level, and causes an interrupt at a very high priority level for the other processing unit via the intercommunication network. The high priority level interrupt causes the other processing unit to execute instructions which load the priority level information from the memory unit and set an interrupt request at the specified level. With both processing units having outstanding interrupt request at the specified priority level, the processing unit which completes all of the processes at priority levels higher or equal to that of the queue entry responds to the interrupt first. By having the least busy processing unit respond to the interrupt utilizing the queue entry to initiate the desired input/output operation process, a balance in the utilization of the input/output processing units is insured.
177 Citations
43 Claims
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1. An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of program processes, said system including a plurality of modules, said modules including at least one memory module and at least a pair of individual input/output processor modules, a host processor module operative to generate signals for specifying initiation of an input/output operation assigned a particular priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:
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a pair of interrupt processing circuit means, one connected to a different one of said pair of input/output processor modules for processing interrupt requests received by the processor module on a priority basis; processor intercommunication network means connected to each of said pair of interrupt processing logic circuits for enabling communication between said pair of processor modules; each of said pair of processor modules comprising; a process control register means for controlling the execution sequence of said program processes, said process control register including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at a predetermined one of a number of different priority levels; and
,control means coupled to receive interrupt request signals from said interrupt logic circuits of said system interface unit associated therewith; said memory module including a plurality of storage locations, a group of said storage locations defining a queue for storing entries designating new processes to be initiated; the interrupt processing circuits of one of said input/output processor modules in response to said signals being operative to apply interrupt request signals to said one processor module, said control means being operative to generate a sequence of signals for switching one of said interrupt bit positions to a predetermined state indicating the presence of an interrupt at said assigned particular priority level, and for storing an entry in said queue of said memory module, and said processor intercommunication means being conditioned by signals of said sequence of signals to apply a high priority type interrupt request signal to the interrupt processing circuits of said other processor module, said circuits conditioning said control means of the other processor module to generate signals for switching one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt at said priority level for enabling the less busy processor module of said pair to initiate said input/output operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of processes, said system including a plurality of modules, said modules including an input/output memory module and a plurality of individual input/output processor modules, a main memory module operative to generate signals for specifying initiation of an input/output operation at a particular priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:
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a plurality of interrupt processing circuit means, each connected to a different one of said plurality of input/output processor modules for processing on a priority basis interrupt requests received by the processor module; intercommunication network means connected to each of said plurality of interrupt processing circuit means for enabling communication between said plurality of processor modules; each of said plurality of processor modules comprising; control register means for controlling the execution sequence of said processes, said control register means including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at one of a number of different priority levels; and
,control means coupled to receive interrupt request signals from said interrupt logic circuit means associated therewith; said input/output memory module including a plurality of storage locations, a group of said storage locations defining a queue for storing entries designating new processes to be initiated; the interrupt processing circuit means of one of said plurality of input/output processor modules in response to said signals from said main memory module being operative to apply interrupt request signals to said one processor module, said control means being operative to generate a sequence of signals for switching of a predetermined one of said interrupt bit positions of said control register means to a predetermined state indicating the presence of an interrupt at said particular priority level and storing an entry in said queue of said input/output memory module, and said intercommunication means being conditioned by signals of said sequence to apply high priority type interrupt request signals to the interrupt processing circuit means of said another one of said plurality of processor modules, said circuit means conditioning said control means of said another processor module to generate signals for switching said predetermined one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt at said particular priority level enabling the least busy processor module of said plurality to initiate said input/output operation thereby balancing the utilization of said input/output processor modules. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of input/output processes, said system including a plurality of modules, said modules including a local memory module, a main memory module and n number of individual input/output processor modules, a host processor module operative to apply to said main memory module connect signals for specifying the initiation of an input/output operation at a designated priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:
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n number of interrupt processing logic circuits, one connected to a different one of said number of input/output processor modules for processing interrupt requests received by the processor module on a priority basis; intercommunication network means connected to each of said number of interrupt processing logic circuits for enabling communication between said number of processor modules; each of said number of processor modules comprising; a process control register for controlling the execution sequence of said processes, said process control register including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at a predetermined one of a number of different priority levels; and
,microprogrammed control means coupled to receive interrupt request signals from said interrupt logic circuits of said system interface unit associated therewith; and said local memory module including a plurality of storage locations, a group of said storage locations and a queue for storing entires designating new input/output processes to be initiated; the interrupt processing logic circuits of a first one of said number of input/output processor modules in response to connect signals from said main memory module being operative to apply interrupt request signals to said first processor module, said microprogrammed control means being operative to generate a sequence of signals for switching of one of said interrupt bit positions to a predetermined state indicating the presence of an interrupt at said designated level and for storing an entry in said queue of said local memory module, and said processor intercommunication means being conditioned by said signals of said sequence to apply high priority type interrupt request signals to the interrupt processing logic circuits of said another one of said number of processor modules, said circuits conditioning said microprogrammed control means of another processor module to generate signals for switching a predetermined one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt request at said designated priority level to enable the least busy processor module of said number to initiate said input/output operation thereby balancing the utilization of said number of input/output processor modules. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification