Monolithically integrated semiconductor circuit arrangement

• US 4,081,792 A
• Filed: 03/26/1976
• Issued: 03/28/1978
• Est. Priority Date: 03/29/1975
• Status: Expired due to Term

• Current Assignee: Licentia Patent-Verwaltungs-GmbH
• Original Assignee: Licentia Patent-Verwaltungs-GmbH
• Inventors: Knapp, Helmut, Rall, Bernhard, Schussler, Hans, Wulf, Hans-Jurgen
• Primary Examiner(s): Pitts, Harold T.
• Application Number:
  US05/670,825
• Time in Patent Office: 732 Days
• Field of Search: 340/166 R, 179/18 GF, 307/239, 307/241
• US Class Current: 340/2.29
• CPC Class Codes: H04Q 3/521 using semiconductors in the switching stages

Abstract

A monolithically integrated semiconductor matrix circuit arrangement comprising switching elements which are connected in pairs at one terminal. This common terminal of the pair of switching elements is connected to an input (or output) circuit path and other terminal of each switching element is connected individually to an output (or input) circuit path respectively.

Claims

1. In a monolithically integrated semiconductor circuit arrangement, particularly for switching matrices of tele-communications switching systems, including a plurality of semiconductor switching elements arranged in a matrix, a plurality of intersecting input and output circuit paths which are arranged in rows and columns and which may be selectively connected together by means of said switching elements, control or triggering means for switching on or blocking said switching elements to selectively connect said input circuit paths to said output circuit paths, and control or triggering lines leading from said control or triggering means to said switching elements, the improvement wherein:

said switching elements are respectively connected in pairs and are arranged between every second input or output circuit path, said switching elements which have been connected together in pairs being connected together to the adjacent input line with one of their terminals and being connected individually to a respective one of the adjacent output lines with their other terminal.

2. A circuit arrangement as defined in claim 1, wherein said control or triggering lines and said control or triggering means for switching on or blocking of the switching elements are arranged in a column between every two columns of said pairs of switching elements in order to increase the screening effect.

3. A circuit arrangement as defined in claim 2, wherein such control means for switching on or blocking of the switching elements comprise monolithically integrated inverter circuits comprise which are arranged in the immediate vicinity of the associated switching elements.

4. A circuit arrangement as defined in claim 3, wherein an inverter circuit is provided for each of the two switching elements in a cross point for balanced transmission.

5. A circuit arrangement as defined in claim 4, further comprising a single crosspoint state store for each crosspoint for controlling the two associated inverters.

6. A circuit arrangement as defined in claim 3, wherein said inverter circuit comprises a driving transistor of the enhancement type and a load transistor of the depletion type.

7. A circuit arrangement as defined in claim 6, wherein an MOS transistor of the depletion type constitutes said load transistor with at least the threshold voltage produced by an ion implantation process.

8. A circuit arrangement as defined in claim 1, wherein said switching elements comprise MOS transistors with a large relationship of channel width to channel length and source and drain regions determining the channel length which are interlaced in meander form.

9. A circuit arrangement as defined in claim 8, wherein said two switching elements connected together with a common electrode terminal comprise a geometric unit.

10. A circuit arrangement as defined in claim 8, wherein said MOS transistors have a ratio of channel width to channel length not substantially below a value of 1000.