Hybrid semiconductor memory with on-chip associative page addressing, page replacement and control
First Claim
1. An associative page addressing system for providing virtual paged stores, comprising:
- a plurality of integrated circuit chips, each said chip containing the storage cells for data, at least one associative circuit including a virtual page address register for receiving and storing the virtual address bits assigned to each page located on one or more chips, and means for comparing a stored virtual address with an interrogate virtual address from a CPU and providing a direct page enable output upon a match thereof;
address decoder means connected to receive said page enable output and locate data addressed in said storage cells; and
Cpu means including a virtual page address register and a real address register, said virtual page address register of said CPU means being connected to said virtual address register on each chip for interrogating said chips when a page request is made, said real address register storing the real address bits which are applied to said address decoder means for selecting a byte of data from said storage cells in the chips;
whereby a matched virtual page address produces an enable output from said comparing means and directly enables the selected chip to be accessed at those locations addressed by said real address register.
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Abstract
An associative system for providing virtual paged stores with on-chip associative address translation and control functions. Each of a plurality of integrated circuit chips contains the storage cells for a unit of data and at least one associative circuit including a virtual page address register for storing the virtual address bits assigned to each page. The CPU includes a virtual page address register and a real address register, with the CPU virtual page address register being connected to the virtual address register on each chip for interrogating the chips when a page request is made. The real address register holds the real address bits for selecting a byte of data from the chips. An interrogate virtual page address is applied to each of the chips for comparison with the address stored in the virtual page address registers, whereby a match will directly enable the selected chip to be read and/or written into. In addition to the virtual page address translation performed directly on the chip, there may also be provided on each chip a page usage information register, a page update register, as well as other control registers for storing page data which is used to determine eligibility of a page for replacement when a page fault is detected.
51 Citations
36 Claims
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1. An associative page addressing system for providing virtual paged stores, comprising:
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a plurality of integrated circuit chips, each said chip containing the storage cells for data, at least one associative circuit including a virtual page address register for receiving and storing the virtual address bits assigned to each page located on one or more chips, and means for comparing a stored virtual address with an interrogate virtual address from a CPU and providing a direct page enable output upon a match thereof; address decoder means connected to receive said page enable output and locate data addressed in said storage cells; and Cpu means including a virtual page address register and a real address register, said virtual page address register of said CPU means being connected to said virtual address register on each chip for interrogating said chips when a page request is made, said real address register storing the real address bits which are applied to said address decoder means for selecting a byte of data from said storage cells in the chips;
whereby a matched virtual page address produces an enable output from said comparing means and directly enables the selected chip to be accessed at those locations addressed by said real address register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A two level, hierarchical storage device for providing a fully associative virtual page address translation function, comprising:
a plurality of integrated circuit chips, each of which includes an associative virtual page address register physically located on chip including both means for receiving and storing the virtual address bits assigned to a page located on one or more chips, and means for comparing a stored virtual address with an interrogate virtual address from a CPU and providing a direct chip or page enable output upon a match thereof for directly enabling a chip memory to be accessed at those locations addressed by the CPU, whereby fully associative compare operations are carried out with all virtual addresses directly on chip. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A two level, hierarchical storage device for providing a fully associative virtual page address translation function, comprising:
a plurality of integrated circuit chips, each of which includes an associative virtual page address register physically located on chip and having both means for receiving and storing the virtual address bits assigned to a page, and means for comparing a stored virtual address with an interrogate virtual address from a CPU and providing a chip or page enable directly on chip, a data storage array on each chip, and address decoder means for locating data addressed in the data storage arrays from the CPU, said chip enable serving to directly enable the data storage array to be accessed at those locations in said address decoder means;
whereby a fully associative virtual page address translation function is provided directly on chip.- View Dependent Claims (34, 35, 36)
Specification