Current to voltage converter

• US 4,086,624 A
• Filed: 06/15/1977
• Issued: 04/25/1978
• Est. Priority Date: 06/15/1977
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Fraley, Phillip Edward
• Primary Examiner(s): Shoop, William M.
• Application Number:
  US05/806,959
• Time in Patent Office: 314 Days
• Field of Search: 307/127, 307/138, 307/255, 307/288, 328/26, 363/127
• US Class Current: 363/127
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Disclosed is a circuit for converting a current input of either polarity to a low voltage output of a single polarity. The circuit includes two pairs of pnp-npn transistors which are coupled to that current flow in one direction will turn on one pair while the other is reverse biased, and the same polarity will appear at the output regardless of the polarity of the input. The low voltage at the output is established by the voltage drop across the transistors of the pair which are conducting. The circuit is particularly suited for converting telephone line current to a voltage output of 1.5 volts or less.

Claims

1. A circuit for converting a current of either polarity at first and second inputs to a fixed voltage of a single polarity across first and second outputs comprising:

a first pair of transistors with a first transistor having its emitter electrically coupled to the first input and its collector electrically coupled to the first output and a second transistor with its collector electrically coupled to the second output and its emitter electrically coupled to the second input, the bases of said first and second transistors being electrically coupled; and

a second pair of transistors with a third transistor having its emitter electrically coupled to the second input and its collector electrically coupled to the first output and a fourth transistor with its emitter electrically coupled to the first input and its collector electrically coupled to the second output, the bases of said fourth and fifth transistors being electrically coupled.

said pairs being coupled so that a different pair is conductive for either of the two polarities of the current at the inputs.

2. The circuit according to claim 1 wherein the bases of the transistors in a pair are electrically coupled so that the voltage at the outputs is determined by the combined voltage across the emitter-base junctions of the conducting pair.

3. The circuit according to claim 1 wherein the first and third transistors each have an emitter of p conductivity type, a base of n conductivity type and a collector of p conductivity type, and the second and fourth transistors have an emitter of n conductivity type, a base of p conductivity type and a collector of n conductivity type.

4. The circuit according to claim 1 further comprising a capacitor coupled across the outputs.

5. A circuit for converting a current of either polarity at first and second input conductors to a fixed voltage of a single polarity across first and second output conductors comprising:

a first pair of transistors with a first transistor having a p-type emitter coupled to the first input conductor, a p-type collector coupled to the first output conductor, and an n-type base directly coupled to a p-type base of a second transistor, said second transistor having an n-type collector coupled to the second output conductor and an n-type emitter coupled to the second input conductor; and

a second pair of transistors with a third transistor having a p-type emitter coupled to the second input conductor, a p-type collector coupled to the first output conductor, and an n-type base directly coupled to a p-type base of a fourth transistor, said fourth transistor having an n-type emitter coupled to the first input conductor and an n-type collector coupled to the second output conductor,

said pairs being coupled so that a different pair is conductive for either of the polarities of the current at the input conductors and the voltage at the output conductors is determined by the combined voltage across the emitter-base junctions of the conducting pair.

6. A circuit for converting a current of either polarity at first and second input conductors to a fixed voltage of a single polarity across first and second output conductors comprising:

a first pair of transistors with a first transistor having a p-type emitter coupled to the first input conductor, an n-type base coupled through a diode to the second input conductor, and a p-type collector coupled to the first output conductor, and a second transistor having an n-type emitter coupled to the second input conductor, a p-type base coupled through a diode to the first input conductor, and an n-type collector coupled to the second output conductor; and

a second pair of transistors with a third transistor having a p-type emitter coupled to the second input conductor, an n-type base coupled through a diode to the first input conductor, and a p-type collector coupled to the first output conductor, and a fourth transistor having an n-type emitter coupled to the first input conductor, a p-type base coupled through a diode to the second input conductor and an n-type collector coupled to the second output conductor,

said pairs being coupled so that a different pair is conductive for either of the polarities of the current at the input conductors.

7. A circuit for inverting a current of either polarity at first and second inputs to a fixed voltage of a single polarity across first and second outputs comprising:

a first pair of transistors with a first transistor having its emitter electrically coupled to the first input and its collector electrically coupled to the first output and a second transistor with its collector electrically coupled to the second output and its emitter electrically coupled to the second input, the emitter-base junctions of said transistors being coupled in parallel with at least one diode coupled in series with the base of each transistor; and

a second pair of transistors with a third transistor having its emitter electrically coupled to the second input and its collector electrically coupled to the first output and a fourth transistor with its emitter electrically coupled to the first input and its collector electrically coupled to the second output, the emitter-base junctions of said transistors being coupled in parallel with at least one diode coupled in series with the base of each transistor,

said pairs being coupled so that a different pair is conductive for either of the two polarities of the current at the inputs and the voltage at the outputs is determined by the voltage across the emitter-base junction and the diode of one transistor in the conducting pair.