Interrupt system for microprocessor system
First Claim
1. A digital data processing system comprising:
- a peripheral device;
a data bus;
memory means coupled to said data bus for storing instructions;
processor means coupled to said data bus for executing instructions stored in said memory means;
adaptor means coupled between said data bus and said peripheral device for transferring data between said data bus and said peripheral device;
a first interrupt conductor coupled to said peripheral device and to said adaptor means;
a second interrupt conductor coupled to said processor means and to said adaptor means;
said processor means including first interrupt means coupled to said second interrupt conductor for effecting addressing of a certain location in said memory means in response to a first interrupt signal on said second interrupt conductor;
said adaptor means including(a) second interrupt means coupled to said first interrupt conductor, to said data bus, and to said second interrupt conductor for producing said first interrupt signal in response to a second interrupt signal produced on said first interrupt conductor by said peripheral device; and
(b) status means responsive to said second interrupt signal coupling said data bus to said second interrupt means for storing information indicative of the occurrence of said second interrupt signal and transferring said information to said processor means via said data bus.
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Abstract
A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.
46 Citations
6 Claims
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1. A digital data processing system comprising:
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a peripheral device; a data bus; memory means coupled to said data bus for storing instructions; processor means coupled to said data bus for executing instructions stored in said memory means; adaptor means coupled between said data bus and said peripheral device for transferring data between said data bus and said peripheral device; a first interrupt conductor coupled to said peripheral device and to said adaptor means; a second interrupt conductor coupled to said processor means and to said adaptor means; said processor means including first interrupt means coupled to said second interrupt conductor for effecting addressing of a certain location in said memory means in response to a first interrupt signal on said second interrupt conductor; said adaptor means including (a) second interrupt means coupled to said first interrupt conductor, to said data bus, and to said second interrupt conductor for producing said first interrupt signal in response to a second interrupt signal produced on said first interrupt conductor by said peripheral device; and (b) status means responsive to said second interrupt signal coupling said data bus to said second interrupt means for storing information indicative of the occurrence of said second interrupt signal and transferring said information to said processor means via said data bus. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification