Scrambler and unscrambler for serial data

• US 4,087,626 A
• Filed: 08/04/1976
• Issued: 05/02/1978
• Est. Priority Date: 08/04/1976
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Brader, Roy Henry
• Primary Examiner(s): Birmiel, Howard A.
• Application Number:
  US05/711,449
• Time in Patent Office: 636 Days
• Field of Search: 178/22, 340/172.5
• US Class Current: 380/42
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
• CPC Class Codes: H04L 9/0656 Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04L 9/34 Bits, or blocks of bits, of the telegraphic message being interchanged in time for speech signals H04K1/06

Abstract

Serial data is scrambled at a transmitting terminal by storing it in sequential locations in a first random access memory, while previously stored information is read out of a second random access memory using a pseudo-random address counter. Whenever one memory is filled and the other memory is emptied, the roles of the memories are transposed. Similar apparatus at a receiving terminal is operated in synchronism and phase to unscramble the received data.

Claims

1. A data reordering system, comprising

first and second random access memories,

a numerical memory address counter providing addresses in numerical sequence,

a pseudo-random memory address counter providing addresses in a pseudo-random sequence,

means to store serial data in said first memory in storage locations determined by one of said address counters while serially reading data out of said second memory from storage locations determined by the other of said address counters, and

means periodically to transpose said first and second memories.

2. A system as defined in claim 1 wherein said means to transpose said memories operates when one memory is filled and the other memory is emptied.

3. A system as defined in claim 1 wherein said means to store data in the first memory uses said numerical address counter while data is read out of said second memory using said pseudo-random address counter, whereby to scramble the serial data at a transmitting terminal.

4. A system as defined in claim 1 wherein said means to store data in the first memory uses said pseudo-random address counter while data is read out of said second memory using said numerical address counter, whereby to unscramble the data at a receiving terminal.

5. A data transmission system, comprising

a serial data scrambler at a transmitting terminal and a serial data unscrambler at a receiving terminal, each including:

two random access memories,

a numerical memory address counter providing addresses in numerical sequence,

a pseudo-random memory address counter providing addresses in a pseudo-random sequence,

means to store serial data in one of said memories in storage locations determined by one of said address counters while serially reading data out of the other of said memories from storage locations determined by the other of said address counters, and

means periodically to transpose the store and read-out operations of said memories using transposed ones of said address counters.

6. A system as defined in claim 5, and in addition a synchronizing and phasing means to cause the translation at the transmitting terminal of data in numerical sequence to data in pseudo-random sequence, at the same time that is causes the translation at the receiving terminal of data in said pseudo-random sequence to data in said numerical sequence.