DTMF Communication system

• US 4,087,638 A
• Filed: 10/01/1976
• Issued: 05/02/1978
• Est. Priority Date: 10/01/1976
• Status: Expired due to Term

• Current Assignee: Telaris Telecommunications Incorporated
• Original Assignee: Telaris Telecommunications Incorporated
• Inventors: Tunzi, Burton Ralph, Hayes, James Christopher
• Primary Examiner(s): Stellar, George G.
• Application Number:
  US05/728,725
• Time in Patent Office: 578 Days
• Field of Search: 179/2 E, 179/41 A, 179/84 VF, 179/90 B, 179/90 K, 328/14, 340/365 S
• US Class Current: 455/564
• CPC Class Codes: H04L 27/30 wherein each code element is represented by a combination of frequencies

Abstract

A highly flexible and economical dual tone multiple frequency (DTMF) communication system includes a data input source such as a keyboard; a repertory dialer or electronic memory; an integratable digital encoder which includes a digital sine wave synthesizer; and a transmission unit such as a radio or a connection to a standard utility telephone system. The digital encoder provides a DTMF output signal at standard telephone frequencies in response to input data and includes a predial delay circuit which allows for dial tone delay or transmitter start up after receipt of data and before generation of an output signal, a two second delay circuit providing a two second output signal which may be utilized to prevent shut down between successive number entries and to lock out noise from a microphone or to a speaker and an automatic number insertion (ANI) circuit. When enabled, the automatic number insertion circuit automatically locks out a keyboard or other data source and transmits a 4 or 8 digit number supplied by a ROM before transmitting keyboard information. The ANI number may be used for automatic dialing, as a station identifier preceeding radio transmissions or as a code key enabling access to restricted information. Additional features provide in even further operator convenience.

Claims

1. A dual tone multiple frequency encoder system comprising:

a keyboard providing data signals indicative of actuated keys;

a data store providing data signals indicative of data characters when addressed;

an encoder circuit coupled to receive sequential data signals from the keyboard and the data store and for each data signal to generate a dual tone multiple frequency signal indicative thereof;

an automatic number insertion circuit coupled to be operative upon receipt of a start signal to sequentially address the data store to generate a plurality of sequential data characters and to inhibit response of the encoder circuit to keyboard data signals only until after said plurality of sequential data characters from the data store have been generated and encoded as dual tone multiple frequency signals;

a start signal circuit coupled to generate a start signal in response to a keyboard key actuation.

2. The encoder system according to claim 1 above, wherein the start signal circuit is further coupled to generate a start signal in response to an external command.

3. The encoder system according to claim 1 above, further comprising means for coupling dual tone multiple frequency signals from the encoder circuit to a telephone network for transmission thereover.

4. The encoder system according to claim 2 above, further comprising a radio transceiver coupled to transmit radio signals carrying dual tone multiple frequency signals generated by the encoder system.

5. The encoder system according to claim 4 above, wherein the transceiver further includes an audio microphone and a push to talk switch coupled to enable the microphone when actuated, and further comprising a circuitry coupled to provide an external command to the start signal circuit in response to actuation of the push to talk switch.

6. The encoder system according to claim 1 above, further comprising a timing circuit coupled to generate a signal 2 SEC RLS which becomes active upon detection of a data signal and which remains active for a period of time following termination of a last data signal.

7. The encoder system according to claim 6 above, wherein the start signal circuit is coupled to generate a start signal only in response to a keyboard key actuation that occurs in the absence of an active 2 SEC RLS signal.

8. The encoder system according to claim 1 above, further comprising a wait circuit coupled to inhibit the generation of keyboard data signals while the automatic number insertion circuit is operative to address the data store.

9. The encoder system according to claim 1 above, further comprising a timing circuit coupled to provide a predial delay by inhibiting response of the encoder system to a first keyboard data signal following a release time period until after a predial period of time has passed.

10. The system according to claim 9 above, wherein the timing circuit is coupled to selectively determine the predial period of time in response to at least one predial delay selection signal.

11. The system according to claim 10 above, wherein one of the selectable predial periods of time is zero.

12. The system according to claim 11 above, wherein one of the selectable predial periods is infinite.

13. The encoder system according to claim 1 above, wherein said encoder circuit includes first and second digital waveform synthesizers digitally generating first and second sinewave signals respectively with different frequencies, said first and second sinewave signals being combined to form said output signal.

14. The encoder system according to claim 13 above, wherein each of said first and second digital frequency synthesizers includes (1) a digital sequencer connected to provide digital output information which indicates a sinewave magnitude at each of a number of successive discrete sinewave phase angles which are approximately equally spaced throughout a sinewave period, said sinewave phase angles for which a magnitude is indicated being incremented in response to a succession of clock pulses;

(2) a digital to analog converter connected to provide a signal magnitude indicative of said digital output information; and

(3) a clock pulse generator connected to respond to said keyboard information by generating a sequence of periodic clock pulses at a frequency equal to an output frequency indicated by said keyboard information multiplied by the number of successive discrete phase angles which are spaced throughout a sinewave period.

15. The encoder system according to claim 1 above, further comprising a power supply circuit that is connectable to provide the encoder system with all electrical operating power requirements thereof in response to electrical power received from a standard utility telephone system connection.

16. The encoder system according to claim 1 above, wherein said encoder circuit includes a first circuit portion having a first power supply input continually coupled to a power supply circuit, a second circuit portion having a second power supply input different from the first, the first circuit portion being operable to generate a power up signal in response to the receipt of keyboard information, and the communication system further comprising means for switching coupled to provide electrical power from the power supply circuit to the second power supply input in response to the power up signal, said second circuit portion consuming no power in the absence of a power up signal.

17. The encoder system according to claim 1 above, wherein said encoder circuit includes means for insuring that tones generated thereby have a predetermined minimum time duration.

18. The encoder system according to claim 17 above, wherein the minimum time duration is 40 milliseconds.

19. The encoder system according to claim 1 above, wherein said encoder circuit includes means responsive to a time limiting signal for limiting tone generation time for any one data signal to a maximum time duration when the time limit signal is active.

20. The encoder system according to claim 19 above, wherein the maximum time duration is 90 milliseconds.

21. The encoder system according to claim 1 above, wherein the encoder circuit includes means for generating an interdigit pulse signal upon completion of the generation of a dual tone multiple frequency signal for each data signal, the interdigit pulse signal being provided as an output signal and also being coupled to the automatic number insertion circuit to command sequencing to a new data character.

22. The encoder system according to claim 1 above, further comprising 16 data input conductors operatively connected to the keyboard and to the data store to receive data signals therefrom and an input decode circuit coupling the data input conductors to the encoder circuit, the input decode circuit being responsive to data format selection signals to convert data signals received by the input conductors from a selected one of a plurality of data formats to a two of eight format.

23. The encoder system according to claim 22 above, wherein the input decode circuit responds to a two of eight data format selection signal by coupling eight of the input conductors directly to the encoder circuit with no code translation.

24. The encoder system according to claim 22 above, wherein the input decode circuit responds to a one of 16 data format selection signal by converting a one of 16 input signal on the input conductors to a two of eight signal.

25. The encoder system according to claim 22 above, wherein the input decode circuit responds to a binary coded number data format selection signal by converting a binary coded number on four of the 16 input conductors to a two of eight signal.

26. The encoder system according to claim 25 above, wherein the input decode circuit includes a 16:

4 multiplexer coupled to provide signals on a selected four of the 16 input conductors for conversion to a two of eight code format.

27. The encoder system according to claim 22 above, further comprising a wrong number of keys detection circuit coupled to generate a wrong number of keys error signal if more than one signal appears on a first group of four conductors coupled to the encoder circuit, if more than one signal appears on a second group of four conductors different from the first group connected to the encoder circuit, or if while a two of eight input data format selection signal is active, a signal does not appear on at least one of a first group of four data input conductors and at least one of a second group of four data input conductors different from the first group.

28. The encoder system according to claim 1 above, further comprising 16 data input conductors operatively coupled to the keyboard and to the data store to receive data signals thereon, and an input decode circuit coupling the data input conductors to the encoder circuit, the input decode circuit including a first gate circuit coupling eight data input conductors to eight data inputs respectively for the encoder circuit only when a two of eight data input format selection signal is active.

29. The encoder system according to claim 28 above, wherein the input decode circuit further includes a 16 to two of eight encoder having 16 input conductors coupled to the 16 data input conductors and eight output conductors and a second gate circuit coupling the eight output conductors of the 16 to two of eight encoder to the eight data inputs respectively for the encoder circuit only when a two of eight data input format selection signal is not active.

30. The encoder system according to claim 29 above, further comprising a third gate coupling the 16 data input conductors to the 16 input conductors of the 16 to two of eight encoder only when a one of 16 input format selection signal is active;

a 16;

4 multiplexer coupled to output signals appearing on one group of four groups of four data input conductors each selected in response to scan signals provided by the automatic number insertion circuit;

a 4;

16 decode matrix coupled to provide one of sixteen signals on 16 output conductors thereof in response to signals output by the multiplexer; and

a fourth gate coupling the sixteen output conductors of the 4;

16 decode matrix to the sixteen input conductors of the 16 to two of eight decoder only when a binary coded number input format selection signal is active, and wherein the automatic number insertion circuit includes means for generating scan signals which command that the four groups of four data input conductors be sequentially coupled to the output of the multiplexer in response to a start signal and to generate a binary coded number input format selection signal in response to a start signal.

31. The encoder system according to claim 30 above, wherein the automatic number insertion circuit generates a first address signal as a first group of four characters are encoded by the system and a second address signal as a second group of four characters are encoded by the system and wherein the data store is coupled to provide a first group of four, four bit binary coded data signals to the 16 input conductors in response to a first address signal and a second group of four, four bit binary coded data signals to the 16 input conductors in response to a second address signal.

32. A dual tone multiple frequency communication sytem comprising

a switch coupling the system to a telephone network;

a microphone coupled to transmit voice frequency signals over a telephone network in response to audible voice frequency signals;

a speaker coupled to generate audible voice frequency signals in response to voice frequency signals received over a telephone network;

a keyboard providing data signals in response to the actuation of keys thereon;

a digital encoder circuit coupled to receive the data signals from the keyboard and to transmit over a telephone network dual tone multiple frequency signals indicative of actuated keys, the digital encoder circuit including means for generating a first signal when a dual tone multiple frequency signal is being generated and means for generating a second signal when a dual tone multiple frequency singal is being generated and for a period of time thereafter;

a muting circuit coupled to reduce the magnitude of audio signals from the speaker in response to a first signal; and

a microphone circuit coupled to block signals from the microphone during the generation of a dual tone multiple frequency signal by the digital encoder circuit and for a period of time thereafter in response to the second signal.

33. The communication system according to claim 32 above, wherein the period of time during which the microphone is blocked following a dual tone multiple frequency signal is approximately 2 seconds.

34. The communication system according to claim 32 above, wherein the digital encoder circuit further includes a timing circuit coupled to provide a predial delay following actuation of a key in the absence of the second signal, the generation of dual tone multiple frequency signals being inhibited during the predial delay.

35. The communication system according to claim 34 above, wherein the digital encoder circuit includes means for selecting a time period from a plurality of selectable time periods in response to predial delay selection signals, the selectable time periods including zero and infinity.

36. The communication system according to claim 35 above, wherein a wait signal is generated during each predial delay period, the wait signal being coupled to disable the keyboard.

37. The communication system according to claim 32 above, further comprising standby and switched power inputs, the standby power input being coupled to provide power to a first portion of the communication system and the switched power input being coupled to provide power to a second portion of the communication system different from the first portion;

a power supply circuit coupled to receive power from a telephone network through the switch and provide power to the standby power input when the switch is closed;

a power up circuit coupled to sense actuation of a keyboard key and to generate a power up signal during actuation of the keyboard key and for a period of time thereafter; and

a switch coupling power from the power supply circuit to the switched power input in response to the power up signal.

38. The communication system according to claim 37 above, wherein the power up circuit includes means for terminating the power up signal in synchronism with termination of the second signal.

39. The communication system according to claim 32 above, wherein the digital encoder circuit further includes a tone duration limit circuit coupled to respond to a tone duration limit input signal by limiting the dual tone multiple frequency signal generated for any given data signal to a predetermined time duration.

40. The communication system according to claim 39 above, wherein the predetermined time duration is greater than 40 milliseconds and less than or equal to 90 milliseconds.

41. The communication system according to claim 32 above, further comprising means for temporarily increasing the input signal.

42. The communication system according to claim 32 above, further comprising means responsive to the first signal for indicating to an operator the availability of the system to accept a new key actuation in the absence of the first signal.

43. The communication system according to claim 37 above, further comprising means responsive to the first signal and to the application of power to the switched power input for indicating to an operator the availability of the system to accept a new key actuation in the absence of the first signal while power is supplied to the switched power input.

44. The communication system according to claim 43 above, wherein said indicating means includes a light emitting diode coupled to indicate the availability of the system to accept a new key actuation when illuminated.

45. A dual tone multiple frequency communication system comprising:

a radio transmitter coupled to transmit audio frequency signals applied to a signal input when enabled by application of an enable signal to an enable input;

a digital encoder circuit generating dual tone multiple frequency signals in response to data input signals and generating a slow release signal that becomes active upon receipt of a data input signal and remains active for a period of time following a last data input signal, the digital encoder to control a data store and in response to a start signal;

a data store coupled to provide data information to the digital encoder circuit under control of the automatic number insertion circuit;

a microphone generating microphone signals indicative of audible signals received thereby;

an actuatable microphone switch; and

an interface circuit coupling dual tone multiple frequency signals to the transmitter signal input when generated by the digital encoder circuit, coupling microphone signals to the transmitter signal input in the absence of the slow release signal, applying an enable signal to the tramsmitter enable input in response to actuation of the microphone switch and in response to the slow release signal and generating a start signal in response to actuation of the microphone switch.

46. The communication system according to claim 45 above, further comprising a keyboard coupled to provide data signals to the digital encoder circuit in response to actuation of keys thereon and means for providing a start signal in response to the actuation of a keyboard key.

47. The communication system according to claim 46 above, wherein said means for providing a start signal is responsive to the slow release signal.

48. The communication system according to claim 45 above, wherein the automatic number insertion circuit includes means responsive to rate selection informaton for sequencing the data input signals at a selected one of a plurality of different rates.

49. The communication system according to claim 48 above, wherein said different rates include 20 data signals per second and 10 data signals per second.

50. The communication system according to claim 45 above, wherein the digital encoder circuit includes means for insuring a minimum time of 40 milliseconds for generation of each dual tone multiple frequency signal.

51. The communication system according to claim 45 above, wherein the digital encoder circuit includes means responsive to a time limit signal for limiting the duration of each dual tone multiple frequency signal to a predetermined time period.

52. The communication system according to claim 51 above, wherein the predetermined time period to which each dual tone multiple frequency signal is limited is approximately 90 milliseconds.

53. The communication system according to claim 45 above, wherein the data store is coupled to provide a first plurality of binary coded information signal groups in response to a first store enable signal and a second plurality of binary coded information signal groups in response to a second store enable signal, and wherein the automatic number insertion circuit includes means for generating a first store enable signal while scanning in sequence the first plurality of binary coded information signal groups and then providing a second store enable signal while scanning in sequence the second plurality of binary coded information signal groups.

54. The communication system according to claim 53 above, further comprising a decoder circuit coupled to convert the binary coded informaton signal groups provided by the data store to two of eight data signals to which the digital encoder circuit responds by generating dual tone multiple frequency signals indicative thereof.

55. The communication system according to claim 45 above, wherein the digital encoder circuit includes means for converting data input signals from a one of sixteen data format to a two of eight data format.

56. The communication system according to claim 45 above, wherein the data store includes a pair of diode matrices.

57. The communication system according to claim 45 above, further comprising means for providing a delay following receipt of a first of a sequence of data input signals before generating a dual tone multiple frequency signal corresponding thereto.

58. A dual tone multiple frequency communication system comprising:

a data unit coupled to provide a sequence of data signals to a digital encoder circuit in response to operator commands; and

a digital encoder circuit coupled to digitally synthesize a dual tone multiple frequency signal corresponding to each data signal, the digital encoder circuit including means for generating an interdigit pulse signal that is coupled to the data unit and indicates completion of each dual tone multiple frequency signal.

59. The communication system according to claim 58 above, wherein the data signals are provided by the data unit in a binary coded format.

60. The communication system according to claim 58 above, wherein the data unit is a repertory dialer.

61. A dual tone multiple frequency communication system comprising:

means for providing data signals; and

a digital encoder circuit coupled to receive the data signals and including a digital waveform synthesizer coupled to digitally synthesize dual tone sinewave signals at frequencies indicative of the data signals, each sinewave signal being synthesized for a minimum period of time notwithstanding earlier termination of a data signal for which a sinewave signal is generated.

62. The communication system according to claim 61 above, wherein the minimum period of time is 40 milliseconds.

63. The communication system according to claim 61 above, further comprising means for limiting the maximum period of time during which each sinewave signal is synthesized.

64. A dual tone multiple frequency communication system comprising:

a source of data signals; and

a digital encoder circuit coupled to respond to a data signal from the source by digitally synthesizing dual tone multiple frequency sinewave signals indicative thereof, the digital encoder providing a selected time delay before commencing the synthesizing of a sinewave signal corresponding to a first of a sequence of data signals.

65. The communication system according to claim 64 above, wherein a new sequence is initiated upon receipt of a data signal by the digital encoder circuit following a release period of time during which no data signal is provided by the source.

66. The communication system according to claim 65 above, wherein the release period of time is approximately 2 seconds.