Valid memory address enable system for a microprocessor system

• US 4,087,855 A
• Filed: 09/17/1975
• Issued: 05/02/1978
• Est. Priority Date: 10/30/1974
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Peddle, Charles I., Wiles, Michael F., Mensch, William D. Jr., Orgill, Rodney H., Carlow, Earl F., Hepworth, Edward C., Bennett, Thomas H., Mathys, Wilbur L.
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/614,109
• Time in Patent Office: 958 Days
• Field of Search: 340/172.5, 445/1, 364/200, 364/900
• US Class Current: 710/100
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence

Abstract

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Claims

1. A digital system comprising:

(a) a peripheral device;

(b) a data bus;

(c) an address bus for conducting binary signals;

(d) processor means coupled to said data bus and to said address bus for executing various instructions;

(e) memory means coupled to said data bus and to said address bus for storing data and storing said instructions, said memory means having a memory enable input;

(f) adaptor means coupled to said data bus, to said address bus, and to said peripheral device for transferring digital information between said peripheral device and said data bus, said adaptor means including an adaptor enable input;

said processor means including

(1) address means coupled to said address bus for generating a binary address on said address bus;

(2) first means for producing an output signal indicative of whether said binary signals on said address bus represent a location being accessed by said processor means; and

(3) an output conductor for conducting said output signal; and

(g) circuit means having an input coupled to said output conductor and having an output coupled to said adaptor enable input of said adaptor means for generating an enable signal in response to said output signal to enable said adaptor means to be accessed by said processor means.

2. The digital system as recited in claim 1 wherein said circuit means is coupled to said memory means to enable said memory means to be accessed by said processor means.

3. The digital system as recited in claim 1 wherein said adaptor means includes an interrupt storage means for storing information representative of an interrupt request by said peripheral device, and also includes means coupled to said interrupt storage means for resetting said interrupt storage means when said adaptor means is accessed.

5. The digital system as recited in claim 1 wherein said processor means is responsive to a clock signal and wherein said circuit means includes an AND-type gate having one input responsive to said clock signal and having another input responsive to said output signal, and having an output coupled to said output of said circuit means.

4. A digital system comprising:

(a) a peripheral device;

(b) a data bus;

(c) an address bus for conducting binary signals;

(d) processor means coupled to said data bus and to said address bus for executing various instructions;

(e) memory means coupled to said data bus and to said address bus for storing data and storing said instructions, said memory means having a memory enable input;

(f) adaptor means coupled to said data bus, to said address bus, and to said peripheral device for transferring digital information between said peripheral device and said data bus, said adaptor means including an adaptor enable input;

said processor means including

(1) address means coupled to said address bus for generating a binary address on said address bus;

(2) first means for producing an output signal indicative of whether said binary signals on said address bus represent a location being accessed by said processor means; and

(3) an output conductor for conducting said output signal; and

(g) circuit means having an input coupled to said output conductor and having an output coupled to said memory enable input of said memory adaptor means for generating an enable signal in response to said output signal to enable said memory means to be accessed by said processor means.