Credit card reader amplifier

• US 4,088,879 A
• Filed: 08/04/1975
• Issued: 05/09/1978
• Est. Priority Date: 08/04/1975
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Banka, Eugene F., Thompson, Roger F.
• Primary Examiner(s): Kilgore, Robert M.
• Application Number:
  US05/601,667
• Time in Patent Office: 1,009 Days
• Field of Search: 235/61.11 D, 235/61.11 E, 235/61.7 R, 235/61.7 B, 307/235, 360/40, 360/41, 360/42, 360/43, 328/110
• US Class Current: 235/449
• CPC Class Codes: G06K 7/0163 by means of additional timing marks on the record-carrier
• CPC Class Codes: G06K 7/084 sensing magnetic material by relative movement detecting flux changes without altering its magnetised state

Abstract

An amplifying device operative to sense changes in the speed of an encoded card as it is being read so as to be able to adjust the reading rate to compensateably follow said changes. The amplifying device is also able to differentially peak sense pulses read thereby disallowing noise transients.

Claims

1. An amplifier system operative to receive a signal from an encoded card reader for differentiably obtaining data clock components from the read signal over a broad band of signal speeds, comprising:

a. means for delaying the signal from the reader and for producing a square wave signal whose transitions correspond to the intersections of the delayed and undelayed signals from the reader;

b. means for delaying the signal from said squaring means and for gating the delayed and undelayed signals from said squaring means to obtain, upon the non-concurrent receipt of either, a digital signal;

c. means initiated by the clock component of the digital signal from said digitizing means for producing a signal whose period is compensated by the speed of the digital signal to be proportional to a predetermined time frame in which probabilistically the data component of the digital signal may occur wherein said signal rate compensation means includes an adjustment circuit means for adjusting the period of the compensated signal over a plurality of clock periods; and

d. gating means responsive to the concurrent receipt of signals from said speed compensation means and said digitizing means for producing a signal indicative that the digital signal from said digitizing means is a data component.

2. The amplifier system of claim 1 wherein said squaring means further includes means for separately amplifying the read signal and the square wave signal.

3. The amplifier system of claim 2 wherein said amplifying means is an operational amplifier.

4. The amplifier system of claim 1 wherein said means for delaying the read signal is a resistive-capacitive circuit.

5. The amplifier system of claim 1 wherein said squaring means is an operational amplifier having a resistive feedback loop which will saturate and output the transition of the square wave when the inputted delayed and undelayed read signals intersect above a threshold level as set by the resistance in the feedback loop.

6. The amplifier system of claim 1 wherein said means for delaying the square wave signal comprises trailing edge delay resistive-capacitive circuit means and leading edge delay resistive-capacitive circuit means for delaying the trailing edge and the leading edge respectively of the square wave of said squaring means.

7. The amplifier system of claim 1 wherein said digitizing means includes an exclusive OR gate.

8. The amplifier system of claim 7 wherein said exclusive OR gate is a plurality of NAND gates.

9. The amplifier system of claim 1 wherein said digitizing means further includes a latch circuit means for engaging the digital signal of said digitizing means to continue being used to trigger on said speed compensation means until a disengaging signal is received from said speed compensation means.

10. The amplifier system of claim 9 wherein said latch circuit means is a pair of cross-connected NAND gates operative to latch on upon receipt of an enabling input to a first of said pair of gates and to latch off when an disenabling input is applied to the other gate.

11. The amplifier system of claim 9 wherein said speed compensation means further includes resistive-capacitive delay circuit means responsive to delay sending the disenabling signal from said speed compensation means to said latch means until sufficient time has elapsed to allow said speed compensation means to fully turn on.

12. The amplifier system of claim 1 further comprises counter means responsive to be incremented by signals from said speed compensation means for outputting after a given plurality of increments an unblocking signal for allowing signals from said speed compensation means and said digitizing means to be received thereafter by said gating means.

13. The amplifier system of claim 12 wherein said counter means further comprises means responsive to a first signal from said speed compensation means to reset said counter means.

14. An amplifier system operative to receive a signal from an encoded card reader for differentiably obtaining data clock components from the read signal over a broad band of signal speeds, comprising:

a. means for delaying the signal from the reader and for producing a square wave signal whose transitions correspond to the intersections of the delayed and undelayed signals from the reader;

b. means for delaying the signal from said squaring means and for gating the delayed and undelayed signals from said squaring means to obtain, upon the non-concurrent receipt of either, a digital signal;

c. means initiated by the clock component of the digital signal from said digitizing means for producing a signal whose period is compensated by the speed of the digital signal to be proportional to a predetermined time frame in which probabilistically the data component of the digital signal may occur wherein said signal rate compensation means includes an adjustment circuit means for adjusting the period of the compensated signal over a plurality of time intervals between clock pulses; and

d. gating means responsive to the concurrent receipt of signals from said speed compensation means and said digitizing means for producing a signal indicative that the digital signal from said digitizing means is a data component, and wherein said speed compensation means further includes input circuit means comprising;

(a) inverting means for reversing the polarity of the digital signal received from said digitizing means; and

(b) resistive-capacitive circuit means for shaping the inverted digital signal to a spike operative to trigger said speed compensation means.

15. The amplifier system of claim 14 wherein said input circuit means further includes a grounded diode means for clamping any positive overshoot of the spike of said resistive-capacitive circuit means as it discharges to ground.

16. The amplifier system of claim 14 wherein said speed compensation means further includes a monostable multivibrator means triggered by the spike of said input circuit means to output a signal related to the signal outputted by said speed compensation means.

17. The amplifier system of claim 16 wherein said monostable multivibrator means is an operational amplifier with resistive-capacitive feedback.

18. The amplifier system of claim 16 wherein said monostable multivibrator means further comprises resistive-capacitive circuit means for providing feedback for setting the period of said monostable multivibrator means.

19. The amplifier system of claim 18 wherein said speed compensation means further included adjustment circuit means responsive to the signal outputted by said monostable multivibrator means for acting to variably bias said resistive-capacitive circuit means of said monostable multivibrator means according to the signal speed of the clock components of the digital signal from said digitizing means for adjustably maintaining the period of the outputted signal of said monostable multivibrator means at a fixed ratio of the period of the clock components.

20. The amplifier system of claim 19 wherein the period of the outputted signal of the monostable multivibrator means is two thirds that of the clock component period of the digital signal.

21. The amplifier system of claim 20 wherein said adjustment circuit means further comprises:

a. means responsive to an outputted signal from the monostable multivibrator means to produce a driving signal; and

b. capacitive means operatively connected to said driver means and said resistive-capacitive circuit means of said monostable multivibrator means for storing a potential proportional to the period that said driver means discharges said capacitive means which will in turn set the next relative charging level of said resistive-capacitive circuit means and thus the period of the output signal of said monostable multivibrator means.

22. The amplifier system of claim 21 wherein said driver means is a transistor.

23. The amplifier system of claim 21 wherein said capacitive means is a grounded capacitor.

24. The amplifier system of claim 21 wherein said adjustment circuit means further comprises:

a. biased resistive-capacitive means operative to be reset by the outputted signal from said monostable multivibrator means for receiving a charge between resets; and

b. diode means operative to be forward biased after said biased resistive-capacitive means have charged without reset for a period analogously equivalent to a given plurality of signals from said monostable multivibrator means for switching on said driver means to dischargably bias said capacitive means to a level sufficient to ensure that after a quiescent state the period of the outputted signal of said monostable multivibrator means will be less than the clock component period of the digital signal.

25. The amplifier system of claim 24 wherein said adjustment circuit means further comprises biased diode means grounded at one end and operative at its other end with said capacitive means, and said resistive-capacitive circuit means of said monostable multivibrator means for providing a charging potential clamp for said capacitive means when it is relatively positive and when said driver means has entered a quiescent state for disallowing astable operation by said monostable multivibrator means in response to said capacitive means approaching ground before said biased resistive-capacitive means can time-out to discharge said capacitive means.

26. The amplifier system of claim 25 wherein said biased diode means is comprised of a plurality of serially connected diodes that are interposably biased.

27. A data identifying apparatus responsive to signals that have been obtained from a digitizer and for distinguishing data pulses from clock pulses in the digitized signal through a relatively wide spectrum of signal rates, comprising:

a. signal rate compensation means triggered by the clock pulse for creating a compensated signal whose period may be adjusted by the clock pulse rate to be proportional to a predetermined time frame in which it is probable that data pulses may occur wherein said signal rate compensation means includes an adjustment circuit means for adjusting the period of the compensated signal over a plurality of time intervals between clock pulses; and

b. gating means operative to receive signals from said signal rate compensation means and said digitizer for outputting upon the concurrent receipt thereof a pulse signifying that the digitized signal is data.

28. The data identifying apparatus of claim 27 wherein said signal rate compensation means is a monostable multivibrator means with resistive-capacitive feedback means for generating the period of the compensated signal as a function of the clock pulse rate acting on said resistive-capacitive feedback means.

29. The data identifying apparatus of claim 28 wherein said adjustment circuit means includes:

a. means responsive to the compensated signal from said monostable multivibrator means for producing a driving signal; and

b. capacitive means operatively connected to said driver means and said resistive-capacitive feedback means for storing a potential that is proportional to the period that said driver means is switched on, and for utilizing the potential level of said capacitive means to set the relative bias level of said resistive-capacitive feedback means to adjust the period of said monostable multivibrator means in accordance with the predetermined time frame if the signal rate should change.

30. The data identifying apparatus of claim 29 further comprising:

a. biased resistive-capacitive means operative to be reset by the compensated signals from said monostable multivibrator means for receiving a charge between resets; and

b. diode means operative to be forward biased after said biased resistive-capacitive means have charged without reset for a period analogously equivalent to a given plurality of compensated signals from said monostable multivibrator means for switching on said driver means to dischargably bias said capacitive means to a level sufficient to ensure that after a quiescent state the period of the compensated signal will be less than the clock pulse period.

31. The data identifying apparatus of claim 30 further comprises biased diode means grounded at one end and operative at its other end with said capacitive means and said resistive-capacitive feedback means for providing a charging potential clamp for said capacitive means when it is relatively positive and when said driver means has entered a quiescent state for disallowing astable operation by said monostable multivibrator means in response to said capacitive means approaching ground before said biased resistive-capacitive means can time-out to discharge said capacitive means.

32. A data amplifying device operatively responsive to digitized signals from an encoded card reader for detecting data pulses from clock pulses in the digitized signal even as the digitized signal rate changes, comprising:

a. monostable multivibrator means operative to be triggered by the clock pulses in the digitized signal for producing a signal having a given period;

b. resistive-capacitive feedback means responsive to the rate of the clock pulses of the digitized signal for providing feedback for setting the period of said monostable multivibrator means;

c. gating means responsive to the digitized signal and the signal of said monostable multivibrator means for outputting a signal upon the concurrent receipt thereof that is indicative that the received digitized signal is a data pulse; and

d. adjustment circuit means for adjusting the period of the compensated signal over a plurality of time intervals between clock pulses, said resistive capacitive feedback means being responsive to the adjustment circuit means.

33. The data amplifying device of claim 32 further comprising:

a. means responsive to the signal from said monostable multivibrator means for producing a driving signal; and

b. capacitive means operatively connected to said driver means and said resistive-capacitive feedback means for storing a potential that is proportional to the period that said driver means is switched on, and for utilizing the potential level of said capacitive means to set the relative bias level of said resistive-capacitive feedback means to adjust the period of said monostable multivibrator means in accordance with the predetermined time frame if the digitized signal rate should change.

34. The data amplifying device of claim 33 further comprising:

a. biased resistive-capacitive means operative to be reset by the signals from said monostable multivibrator means for receiving a charge between resets; and

b. diode means operative to be forward biased after said biased resistive-capacitive means have charged without reset for a period analogously equivalent to a given plurality of signals from said monostable multivibrator means for switching on said driver means to dischargably bias said capacitive means to a level sufficient to ensure that after a quiescent state the period of the signal from said monostable multivibrator means will be less than the clock pulse period.

35. The data amplifying device of claim 34 further comprises biased diode means grounded at one end and operative at its other end with said capacitive means and said resistive-capacitive feedback means for providing a charging potential clamp for said capacitive means when it is relatively positive and when said driver means has entered a quiescent state for disallowing astable operation by said monostable multivibrator means in response to said capacitive means approaching ground before said biased resistive-capacitive means.

36. A method for distinguishing a data component from a clock component of a digitized signal read from an encoded card over a wide spectrum of digitized signal rates, said method comprising the steps of:

a. producing a signal upon being initiated by the clock component, whose period may be adjusted over a plurality of time intervals between clock pulses to be proportional to a predetermined time frame in which it is probable that data components may occur; and

b. gating the digitized signal with the adjusted signal to obtain, upon the concurrent receipt thereof, a signal indicating that the digitized signal is a data component.

37. A method of differentiably obtaining data and clock components from a signal read from an encoded card over a wide range of signal rates, said method comprising the steps of:

a. delaying the read signal;

b. producing a square wave signal whose transitions correspond to the intersections of the delayed and undelayed read signals;

c. delaying the square wave signal;

d. exclusive OR gating the delayed and undelayed square wave signals to obtain a digitized signal upon the non-concurrent receipt thereof;

e. creating a signal, upon being initiated by the clock component of the digitized signal, whose period may be adjusted over a plurality of time intervals between clock pulses to be proportional to a predetermined time frame in which it is probable that data components may occur; and

f. AND gating the digitized signal with the adjusted signal to obtain, upon the concurrent receipt thereof, a signal indicating that the digitized signal is a data component.