Memory apparatus with defective modules

• US 4,089,063 A
• Filed: 04/08/1977
• Issued: 05/09/1978
• Est. Priority Date: 04/12/1976
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kanie, Takashi, Takezono, Takashi
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/785,825
• Time in Patent Office: 396 Days
• Field of Search: 340/173 BB, 235/153 AM
• US Class Current: 365/200
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A module array has a plurality of memory modules, each having at least one memory cell, arranged in a matrix of m rows and n columns. An address input provides row addresses for each column of the array from outside the memory apparatus. Address modification devices for each column of the module array modify the row addresses provided for each column of the array to provide new addresses. Address decoders in the array are connected to the address modification devices for selecting the modules of each column of the array, one by one, in accordance with the new addresses. A module state indicator in the array is connected to the address decoders and has memories of at least one bit corresponding to each module of all the rows and all the columns of the array, except one border column for indicating the good or defective condition of each module when accessed at the time the module is accessed. A module selector is connected to the module state indicator and to the array for selecting only a specified number of good modules from n modules accessed simultaneously according to the indication of the module state indicator. Input-output devices are connected by the module selector to the good modules selected by the module selector.

Claims

1. Memory apparatus, comprising

a module array having a plurality of memory modules, each having at least one memory cell, arranged in a matrix of m rows and n columns;

address input means for providing row addresses for each column of the array from outside said memory apparatus;

address modification means for each column of the module array for modifying the row addresses provided for each column of the array to provide new addresses;

address decoding means in the array connected to the address modification means for selecting the modules of each column of the array, one by one, in accordance with the new addresses;

module state indicator means in the array connected to the address decoding means and having memory means of at least one bit corresponding to each module of all the rows and all the columns of the array, except one border column, for indicating the good or defective condition of each module when accessed at the time the module is accessed;

module selection means connected to the module state indicator means and to the array for selecting only a specified number of good modules from n modules accessed simultaneously according to the indication of the module state indicator; and

input-output means connected by the module selection means to the good modules selected by the module selection means.

2. Memory apparatus as claimed in claim 1, wherein the module selection means comprises α

multiplier circuit means connected in series with each other and connected to the module state indicator means of each column of the array for providing for each column of the array an output directly corresponding to a Galois field element α

ⁱ supplied from the next-preceding stage when the indication of the module state indicator is for a good module and an output corresponding to a Galois field element α

ⁱ⁺¹ when the indication of the module state indicator is for a defective module, and demultiplexer circuit means connected to each column of the array and to the α

multiplier circuit means for controlling the connection of an accessed module in a column of the array to the input-output means in accordance with the output of the α

multiplier circuit means corresponding to the column and indication of the module state indicator.

3. Memory apparatus as claimed in claim 1, wherein the module selection means comprises adder circuit means connected in series with each other and connected to the module state indicator means of each column of the array for providing for each column of the array an output directly corresponding to the binary value supplied from the next-preceding stage when the indication of the module state indicator is for a good module and an output corresponding to said binary value plus +1 when the indication of the module state indicator is for a defective module, and demultiplexer circuit means connected to each column of the array and to the adder circuit means for controlling the connection of an accessed module in a column of the array and to the input-output means in accordance with the output of the adder circuit means corresponding to the column and indication of the module state indicator.

4. Memory apparatus as claimed in claim 3, further comprising control means for controlling the module selection means to select good modules in accordance with a selected part of each memory module.

5. Memory apparatus as claimed in claim 4, wherein the selected part of each memory module controlled by the control means is the whole module.

6. Memory apparatus as claimed in claim 4, wherein the selected part of each memory module controlled by the control means is a fraction of the module.

7. Memory apparatus as claimed in claim 1, further comprising a sheet of a semiconductor wafer, and wherein the module array is provided on said sheet.

8. Memory apparatus as claimed in claim 1, further comprising a plurality of read only memory lines each having an input end with a read only memory write terminal connected thereto and an output end connected to the module selection means, and connected to the module state indicator means of a corresponding one of the columns of the array.