Integrated circuit fusing technique

• US 4,089,734 A
• Filed: 02/03/1977
• Issued: 05/16/1978
• Est. Priority Date: 09/16/1974
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Bierig, Robert W.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US05/765,496
• Time in Patent Office: 467 Days
• Field of Search: 29/573, 29/580, 29/591, 29/623, 29/577, 29/574, 156/652, 156/659, 156/654-657, 156/901, 427/88-91, 357/51, 357/68, 357/71, 357/28, 204/192
• US Class Current: 438/601
• CPC Class Codes: G01S 13/426 Scanning radar, e.g. 3D radar G01S13/66 takes precedence
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/32188 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: Y10T 29/49107 Fuse making

Abstract

A fusing technique whereby a fuse is fabricated upon a substrate by integrated circuit techniques. Three or more layers of chemically dissimilar metals are deposited upon the region where the fuse is to be formed. The top layers are then etched away from the region where the fusible link is to be formed leaving the lower two layers, the top one of which forms the actual fusible link. The lower layer is then etched away leaving the fusible link suspended from the underlying substrate. The current necessary to cause such a fuse to blow is consistent from fuse to fuse since the physical dimensions of the fusible link can accurately be controlled with the integrated circuit techniques used and, since the fusible link is not in contact with the substrate, the rate at which heat is conducted away from the fusible link cannot vary from fuse to fuse. The method is used to advantage in microwave power and oscillator diode circuits such as those used in phased array radar systems and in read only memories and memory reconfiguration applications, as well as other semiconductor fusing applications.

Claims

1. The method of producing an integrated circuit fuse comprising the steps of:

depositing a first conductive layer upon a substrate in contact with at least two circuit elements;

depositing a second conductive layer upon said first conductive layer coextensive with said first conductive layer, said second conductive layer comprising a material different from the material of said first conductive layer; and

removing a portion of said first layer between said substrate and said second conductive layer to form a fusible link from portions of said second conductive layer having planar surfaces and a uniform cross section, said portion extending across said first conductive layer.

2. The method of claim 1 wherein said depositing a first conductive layer and said depositing a second conductive layer comprise sputtering metal.

3. The method of claim 2 wherein said first layer comprises titanium and said second layer comprises platinum.

4. The method of claim 1 further comprising the steps of:

depositing a third conductive layer upon said second conductive layer coextensive with said first and second conductive layers; and

removing a portion of said third conductive layer coextensive with the removed portion of said first conductive layer.

5. The method of claim 1 further comprising the step of coupling said first conductive layer to components within said substrate.

6. The method comprising the steps:

depositing a first layer of titanium onto a substrate;

depositing a second layer of platinum onto said first layer;

depositing a third layer of gold onto said second layer;

depositing a fourth layer of titanium onto said third layer;

oxidizing a portion of the surface of said fourth layer;

etching away said fourth layer of titanium under that portion of said surface of said fourth layer of titanium which was not oxidized;

etching away said third layer of gold in a region coextensive with the etched away portion of said fourth layer of titanium; and

etching away said first layer of titanium in a region coextensive with said etched away portion of said fourth layer of titanium.

7. The method of claim 6 further comprising etching away a portion of said substrate.

8. The combination of claim 6 wherein said first layer of titanium is deposited in electrical contact with one or more semiconductor devices within said substrate.