Complementary symmetry FET mixer circuits
First Claim
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1. A mixer comprising, in combination:
- first and second terminals between which an operating voltage may be applied;
a circuit output terminal;
six field effect transistors, first and second and third of these transistors being of a first conductivity type and fourth and fifth and sixth of these transistors being of a second conductivity type complementary to said first conductivity type, each transistor having a conduction path between input and output electrodes and having a control electrode, the conduction paths of said first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of said fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal;
means for quiescently biasing all of said transistors in the linear region of their operating range including;
means for applying similar quiescent potentials to the control electrodes of said first and fourth transistors thereby to connect them as a first complementary conduction pair,means for applying similar quiescent potentials to the control electrodes of said second and fifth transistors thereby to connect them as a second complementary conduction pair, andmeans for applying similar quiescent potentials to the control electrodes of said third and sixth transistors, thereby to connect them as a third complementary conduction pair;
means for applying a first input signal at frequency f1 to the control electrodes of said first and fourth transistors;
means for applying a second input signal at frequency f2 to the control electrodes of said second and fifth transistors; and
a tuned output circuit coupled between said output terminal and another circuit point, said circuit being tuned to the one of the output signal frequency components of interest available at said output terminal.
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Abstract
Series-connected, field-effect transistors (FET'"'"'s) of complementary conductivity types are employed to mix two or more input signals. The transistors are quiescently biased in their linear operating range. Each input signal is applied to the gate electrode of one FET and the gate electrode of the corresponding FET of opposite conductivity type in the series string. The output signal containing sum and difference frequencies is available at a common drain connection between two adjacent transistors of opposite conductivity types at the center of the string.
15 Citations
17 Claims
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1. A mixer comprising, in combination:
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first and second terminals between which an operating voltage may be applied; a circuit output terminal; six field effect transistors, first and second and third of these transistors being of a first conductivity type and fourth and fifth and sixth of these transistors being of a second conductivity type complementary to said first conductivity type, each transistor having a conduction path between input and output electrodes and having a control electrode, the conduction paths of said first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of said fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal; means for quiescently biasing all of said transistors in the linear region of their operating range including; means for applying similar quiescent potentials to the control electrodes of said first and fourth transistors thereby to connect them as a first complementary conduction pair, means for applying similar quiescent potentials to the control electrodes of said second and fifth transistors thereby to connect them as a second complementary conduction pair, and means for applying similar quiescent potentials to the control electrodes of said third and sixth transistors, thereby to connect them as a third complementary conduction pair; means for applying a first input signal at frequency f1 to the control electrodes of said first and fourth transistors; means for applying a second input signal at frequency f2 to the control electrodes of said second and fifth transistors; and a tuned output circuit coupled between said output terminal and another circuit point, said circuit being tuned to the one of the output signal frequency components of interest available at said output terminal. - View Dependent Claims (2, 3, 4, 8)
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5. A mixer comprising, in combination:
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first and second terminals between which an operating voltage may be applied; a circuit output terminal; six MOS transistors, the first and second and third of P-type and the fourth and fifth and sixth of N-type, each transistor having a conduction path between source and drain electrodes and having a gate electrode, the conduction paths of the first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of the fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal; means for quiescently biasing the gate electrodes of the first and fourth transistors at a voltage level such that each operates in the linear region of its operating range whereby the first and fourth transistors operate as a first complementary conduction pair; means for quiescently biasing the gate electrode of said second and fifth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the second and fifth transistors operate as a second complementary conduction pair; means for quiescently biasing the gate electrodes of said third and sixth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the third and sixth transistors operate as a third complementary conduction pair; a first parallel tuned circuit, tuned to frequency f1, connected at one terminal to AC ground and at its other terminal to the gate electrodes of said first and fourth transistors; means for introducing a signal at frequency f1 to said first circuit; a second parallel tuned circuit, this one tuned to frequency f2, connected at one terminal to AC ground and at its other terminal to the gate electrodes of said second and fifth transistors; means for introducing a signal at frequency f2 to said second circuit; and a third parallel tuned circuit tuned to one of the frequency components present at said output terminal connected between said output terminal and AC ground. - View Dependent Claims (6, 7, 9)
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10. A mixer comprising, in combination:
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first and second terminals between which an operating voltage may be applied; a circuit output terminal; first and second field effect transistors of a first conductivity type having respective conduction paths in a series connection between said first terminal and said output terminal and having respective gate electrodes; third and fourth field effect transistors of a second conductivity type having respective conduction paths in a series connection between said second terminal and said output terminal and having respective gate electrodes, said first and said second conductivity types being complementary to each other; means for quiescently biasing said first and second and third and fourth transistors in the linear region of their operating range including means for applying similar quiescent potentials to the gate electrodes of said first and third transistors thereby to connect them as a first complementary conductivity pair, and means for applying similar quiescent potentials to the control electrodes of said second and fourth transistors thereby to connect them as a second complementary conduction pair; means for applying a first input signal at frequency f1 to the gate electrodes of said first and third transistors; means for applying a second input signal at frequency f2 to the gate electrodes of said second and fourth transistors; and an output circuit coupled between said output terminal and said circuit point, for selecting one of the sum and difference frequencies of f1 and f2 available responsive to f1 and f2. - View Dependent Claims (11, 12, 13, 14)
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15. A cascode configuration comprising:
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means for supplying an input signal potential; first and second terminals for receiving an operating voltage therebetween; a signal output terminal; first and second n-channel field effect transistors of the enhancement mode type and first and second p-channel field effect transistors of the enhancement mode type, each of said field effect transistors having source and drain and gate electrodes, the source electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to said first terminal and to said second terminal, the drain electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to the source electrode of said second n-channel transistor and to the source electrode of said second p-channel transistor, the drain electrodes of said second n-channel transistor and of said second p-channel transistor being connected to said output terminal; low-pass filtering network means having an input connection to which said output terminal connects and having first and second output connections for providing first and second direct bias potentials each equal to the quiescent potential at said output terminal, said second output connection connected to the gate electrodes of said second n-channel and second p-channel transistors to apply said second direct bias potential to each of them; means for additively combining said input signal potential with said first direct bias potential to provide a potential to the gate electrodes of said first n-channel and first p-channel transistors. - View Dependent Claims (16, 17)
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Specification