Vital digital communication system

• US 4,090,173 A
• Filed: 12/17/1976
• Issued: 05/16/1978
• Est. Priority Date: 12/17/1976
• Status: Expired due to Term

• Current Assignee: Sasib SpA (Is Company SRL)
• Original Assignee: General Signal Corporation (SPX Corporation)
• Inventors: Sibley, Henry C.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/751,505
• Time in Patent Office: 515 Days
• Field of Search: 340/146.1 BA, 340/146.1 AB
• US Class Current: 714/37
• CPC Class Codes: G06F 11/1625 in communications, e.g. transmission, interfaces
• CPC Class Codes: G08C 25/00 Arrangements for preventing or correcting errors; Monitoring arrangements
• CPC Class Codes: H03M 13/51 Constant weight codes; n-out-of-m codes; Berger codes
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00

Abstract

An all-digital communication system is arranged to exhibit fail-safe qualities. Each message includes a pair of words, each word separated from every other word by framing information in the form of two bits, either 1/0 or 0/1. Each word in the message is arranged to exhibit a constant ratio of 1'"'"'s to 0'"'"'s, so that more than a single change in any bit location is needed to change from one valid message word to another. The second word in each message is the complement of the first. Two decoders are disclosed, a hard-wired embodiment and an embodiment employing a microprocessor. In the hard-wired embodiment, straightforward decoding is employed to determine the apparent message, and the apparent message is encoded to generate a locally generated message which is then compared, bit by bit, with the received message employing vital logic techniques. Assuming each of the received and locally generated bits compare, the message is validated.

In the microprocessor embodiment, decoding of each word is accomplished by a table. Several checks are run to determine that the microprocessor is operating properly. The checks if successfully completed, produce a check word, which is not stored in the machine. The check word generated by decoding of the second word of a message should be complement of the first check word. External hardware determines the existence of each check word, in sequence, and allows the decoded microprocessor output to be effective.

Claims

1. Vital digital communication system responsive to the selection of a desired command to be sent for encoding a corresponding message, transmitting and decoding the message to derive said command in a vital manner comprising:

a transmitter including encoding means responsive to the selection of a desired command for generating and outputting said message, said message comprising a pair of multi-bit words, each word separated from other words by an identical multi-bit framing sequence, a second word of said pair complementary to a first word of said pair, the ratio of ones and zeroes in either said first or second word being constant,

a receiver including vital decoding means responsive to the output of said encoder for identifying said framing bits and for identifying each word of said message, said vital decoding means including,

means for sequentially producing multi-bit words in response to sequential receipt of said encoded words and means for checking that said sequentially produced multi-bit words are complementary to each other, said last-named means including,

a multi-bit comparator for comparing said produced multi-bit word with a multi-bit pattern, said comparator sequentially emitting different outputs if sequential ones of said produced multi-bit words are complementary, said vital decoding means providing an output indicative of said command if, and only if, said sequentially emitted outputs are provided.

2. The apparatus of claim 1 wherein said encoding means includes

a clock

shift register loading means,

a shift register coupled to said clock, said shift register responding to said shift register loading means for alternately storing in said shift register a pair of framing bits and an encoded word or its complement, said shift register outputing said message in response to said clock.

3. The apparatus of claim 2 in which said shift register loading means includes

a plurality of bit pattern producing means, each corresponding to a different message that can be sent, a different one of said bit pattern producing means enabled by said selection of a desired command.

4. The apparatus of claim 3 in which each of said bit pattern producing means includes a coupling means coupling a selected potential to a word or complement terminal for each bit in said bit pattern,

word and complement switching means responsive to said clock for alternately coupling said word or complement terminals to a different selected potential to generate a bit pattern or its complement in response to said clock at terminals of said coupling means.

5. The apparatus of claim 1 wherein said vital decoding means includes,

a register for sequentially storing sequentially received words,

combining means for combining various bit positions outputs of said register in selected combinations for identifying an apparent message,

said means for sequentially producing multi-bit words in response to receipt of said encoded words including encoding means responsive to said apparent message for locally generating a bit pattern corresponding to said apparent message,

said produced word compared by said multi-bit comparator comprising said received word and said multi-bit pattern with which said produced word is compared comprising said locally generated bit pattern.

6. The apparatus of claim 1 wherein said vital decoding means includes a register for sequentially storing received words,

a decoding panel for each possible message,

each said panel including two series of serially connected gates, each of said gates in a series connected to a different stage of said register, the connections of corresponding gates, in each series, to said register being complementary, and

output means connected to an output of a last gate of each series of gates for providing a distinctive output if a message word and its complement are alternately stored in said register.

7. The apparatus of claim 1 wherein said vital decoding means includes a single central processor unit responsive to said message for producing an output distinctive of said message,

and wherein said multi-bit comparator compares said produced multi-bit word comprising a check word provided by said central processing unit to validate the operations thereof.

8. The apparatus of claim 7 wherein said central processor unit includes:

first checking means to check operation of at least one output port of said central processor unit, said first checking means producing a quantity,

said central processor unit employing said quantity in deriving said check word.

9. The apparatus of claim 7 in which said central processor unit includes,

means responsive to a received message word for modifying said word in a predetermined fashion and for using said modified message word in deriving said check word.

10. The apparatus of claim 7 in which said central processor unit includes:

means for decoding said message and writing a signal distinctive thereof in an output port,

input means responsive to said signal in said output port for accessing a table and deriving a quantity therefrom, and

means employing said quantity in deriving said check word.

11. The apparatus of claim 7 in which said central processor unit includes:

first checking means to check operation of at least one port of said central processor unit, said first checking means producing a first quantity,

means responsive to a received message word for modifying said word in a predetermined fashion to produce a modified message word,

means for decoding said message and writing a signal distinctive thereof in an output port,

input means responsive to said signal in said output port for accessing a table and deriving a second quantity therefrom,

second checking means producing said check word as the sum of said first quantity, said modified message and said second quantity.

12. A vital decoder for a digital communication system in which one multi-bit message of a plurality of messages is repetitively transmitted in serial form, said multi-bit message including two words, a second complementary to a first, each word having a constant ratio of 1'"'"'s to 0'"'"'s and words separated by an identical multi-bit framing pattern, said decoder comprising:

register means into which a received message is clocked, bit by bit,

frame detector means coupled to said register means,

a storage register also coupled to said register means and controlled by said frame detector means for storage of a message word,

apparent message determining means responsive to said storage register and coupled to output means, for generating an apparent message,

encoding means responsive to said apparent message determining means for generating a locally encoded message corresponding to said apparent message,

and vital logic means responsive to both said storage register and to said apparent message for enabling said output means,

said vital logic means including a multi-bit comparator comparing received words from said storage register and corresponding words from said encoding means and producing two distinctive sequential outputs if said words are identical,

said vital logic means enabling said output means if, and only if, said multi-bit comparator produces said two distinctive outputs, alternately and in sequence.

13. The apparatus of claim 12 further including a pair of voltage generators producing potentials greater in absolute value than any supply potential in response to one or another of said distinctive outputs of said multi-bit comparator, said multi-bit comparator is coupled to both said vital driving means,

each said vital driving means producing said potential responsive to the corresponding multi-bit comparator output,

each said vital driving means having a capacitively coupled output.

14. The apparatus of claim 13 in which each said vital driving means is coupled to further logic means producing a distinctive signal if, and only if, both said vital driving means produce said DC potentials, said distinctive signal enabling said output means.

15. A vital decoder for a digital message which digital message includes a pair of multi-bit words separated from other words by a predetermined multi-bit framing sequence, a second word of said message complementary to a first word, said decoder including a single central processing means, said central processing means including:

means responsive to said framing sequence for identifying each multi-bit word;

means responsive to each said multi-bit word for determining a command represented thereby;

checking means for checking control of said central processing means over its own output ports, said checking means producing one of two distinctive multi-bit words in response to completion of said checking after receipt of each said message word, said distinctive multi-bit words being complementary if said message words are valid and said checks are favorable, said decoder further including;

logic means responsive to said distinctive multi-bit words for validating operation of said central processing means,

said logic means including a multi-bit comparator for comparing said distinctive words to predetermined bit patterns and validating said operation if, and only if, said distinctive words are produced alternately and in sequence, and

means responsive to validation by said logic means for enabling utilization of a command provided by said central processing means.

16. The apparatus of claim 15 which further includes isolation means coupling outputs of said central processing means to inputs thereof, said outputs coupled through said isolation means to said inputs with a right shift said checking means setting the lowest order output bit, and cyclically reading output to input and writing input to output until the lowest order output is again set, said checking means further recording the number of cycles employed and using said number in producing said distinctive multi-bit words.

17. The apparatus of claim 15 in which said central processing means modifies each multibit word, derives, from a table, a numerical quantity corresponding to said modified multibit word, and uses said numerical quantity in producing said distinctive multibit word.

18. The apparatus of claim 15 in which said central processing means writes a digital version of said command to several bit outputs, reads in a modified version thereof, employs said modified version, with a table, to derive a numerical quantity used to produce said distinctive multibit word.