Synchronous digital data scrambling system

• US 4,091,423 A
• Filed: 03/17/1975
• Issued: 05/23/1978
• Est. Priority Date: 03/17/1975
• Status: Expired due to Term

• Current Assignee: Datotek Incorporated
• Original Assignee: Datotek Incorporated
• Inventors: Branscome, Kenneth M.
• Primary Examiner(s): Buczinski, S. C.
• Application Number:
  US05/559,389
• Time in Patent Office: 1,163 Days
• Field of Search: 178/5.1, 178/22, 178/69.5 F, 178/69.1, 325/122, 325/32, 235/181, 358/256, 358/259, 358/261, 358/262, 358/263, 358/141, 358/260
• US Class Current: 380/244
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
• CPC Class Codes: H04L 9/0656 Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04N 1/448 Rendering the image unintelligible, e.g. scrambling
• CPC Class Codes: H04N 1/4486 using digital data encryption

Abstract

The specification discloses a system for scrambling digital signals transmitted between a synchronous data transmitting station and a receiving station. When the scrambling system is used with a facsimile system, a first scrambler is connected between the video amplifier and the transmitter modulator of the transmitting facsimile station. The first scrambler includes digital circuitry for digitizing the output of the video amplifier and enciphering circuitry for enciphering the digitized output of the video amplifier and for transmitting the enciphered output to the receiving facsimile station. A second scrambler is connected between the demodulator and the write amplifier of the receiving facsimile station. The second scrambler includes deciphering circuitry for deciphering the output of the demodulator and for applying the deciphered output to the write amplifier to provide a duplicate of the transmitted facsimile material. Initialization between the first and second scrambler is accomplished with the use of correlation and prime patterns. Circuitry is provided to maintain the first and second scramblers in synchronization with one another, and alarm systems are provided to indicate malfunction of the scramblers and to prevent the transmission of sensitive data in the unciphered state.

Claims

1. A system for scrambling facsimile signals transmitted between a transmitting facsimile station and a receiving facsimile station comprising:

first scrambling means for being connected between the video amplifier and the transmitter of said transmitting facsimile station,

means for generating a randomized digital keystream,

means for selectively varying said randomized digital keystream,

said first scrambling means including digitizing circuitry for digitizing the output of said video amplifier and further including enciphering means for enciphering said digitized output of said video amplifier according to said randomized digital keystream and for transmitting said enciphered digitized output through said transmitter to said receiving facsimile station,

second scrambling means for being connected between the demodulator and write amplifier of said receiving facsimile station,

said second scrambling means including deciphering means for deciphering the enciphered output of said demodulator and for applying the deciphered output to said write amplifier to provide a duplicate of the transmitted facsimile material.

2. The scrambling system of claim 1 and further comprising:

means for directing said digital enciphered output to an internal modem of said transmitting facsimile station,

means for being selectively connected to an external modem for directing said digital enciphered output to an external modem if increased resolution is desired.

3. The system of claim 1 and further comprising:

means in said first scrambling means for generating correlation signals, and

means in said second scrambling means responsive to said correlation signals for synchronizing with said first scrambling means.

4. The system of claim 3 wherein said correlation signal comprises a predetermined digital coded sequence.

5. The system of claim 3 and further comprising prime generating means in said first scrambling means for generating a random prime sequence subsequent to said correlation signal, and

means in said second scrambling means for detecting said prime sequence in order to synchronize said scrambling means.

6. The system of claim 5 wherein said prime generating means comprises:

means for generating a random prime digital sequence, and

circuitry responsive to said prime digital sequence for selectively inverting said correlation signals.

7. A scrambler system for synchronous digital data transmission comprising:

means for generating a randomized digital keystream,

means for selectively varying said randomized digital keystream,

synchronizing means at a first location for generating a predetermined digital correlation pattern followed by a predetermined digital prime sequence, wherein said prime sequence comprises a series of said correlation patterns with ones of said patterns being selectively inverted in accordance with said randomized digital keystream,

means for digitizing data and enciphering data according to said randomized digital keystream and for transmitting said digital enciphered data,

correlation detection means at a second location for detecting said digital correlation patterns and digital prime sequence,

receiving means responsive to said correlation detection means for receiving and deciphering said digital enciphered data contemporaneously with said enciphering and transmission of said digital data, and

means for preventing said receiving means from deciphering said digital enciphered data unless said correlation pattern and said prime sequence meet predetermined accuracy criteria.

8. The scrambler system of claim 7 and further comprising:

means for generating a series of clock phase acquisition pulses prior to generation of said correlation pattern.

9. In a scrambler for a facsimile transmission system having a first facsimile station for enciphering clear facsimile data according to a randomized digital keystream and transmitting enciphered digital data to a second facsimile station for deciphering the enciphered digital data to provide received digital clear facsimile data, an out of synchronization detector comprising:

means for counting up when adjacent bits of the received digital clear facsimile data are alike and for counting down when adjacent bits of the received digital clear facsimile data are not alike, and

means for generating an out of synchronization signal when said counting means counts to a predetermined level.

10. The detector of claim 9 wherein said facsimile transmission system includes a duplex channel and further comprising:

means for generating a signal from said second facsimile station through said duplex channel to said first facsimile station for terminating transmission of said enciphered digital data when said counting means counts to said predetermined level.

11. The detector of claim 9 wherein said means for counting counts up four counts and counts down five counts.

12. the detector of claim 9 wherein said means for counting comprises a synchronous up/down counter.

13. A scrambler for use with a digital synchronous data transmission system comprising:

means for generating a randomized digital keystream,

means at a first location for enciphering clear data according to a randomized digital keystream and for transmitting enciphered digital data to a second location, said means operating in accordance with a first predetermined internal clock signal,

means at said second location for deciphering said scrambled digital data in accordance with a second internal clock signal,

phase lock loop circuitry responsive to said enciphered digital data and said second internal clock signal for generating addition and subtraction signals, and

means responsive to said addition and subtraction signals for varying said second internal clock signal to maintain said first and second clock signals in synchronism.

14. The scrambler of claim 13 wherein said means for varying adds or subtracts pulses from said second internal clock signal.

15. The scrambler of claim 13 wherein said digital data comprises digital facsimile information.

16. The scrambler of claim 15 wherein said means for varying adds or subtracts pulses from said second internal clock signal.