Input/output maintenance access apparatus

• US 4,091,455 A
• Filed: 12/20/1976
• Issued: 05/23/1978
• Est. Priority Date: 12/20/1976
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Porter, Marion G., Monahan, Earnest M., Woods, John M.
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/752,345
• Time in Patent Office: 519 Days
• Field of Search: 364/200, 235/153 AK
• US Class Current: 714/25
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/2294 by remote test

Abstract

An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit. The other circuits within the system interface unit in response to a further command condition certain switching circuit networks for loading the status signals into one of the registers included in the system interface unit for subsequent analysis by system routines.

Claims

1. A data processing system including a plurality of modules, said plurality of modules including at least a pair of input/output processing units, each processing unit including a plurality of storage elements including a number of control registers for storing status and control information required for program processing, data output means operatively coupled to said number of control registers for read out of the contents of said number of registers and clocking circuits for generating timing signals for enabling said input/output processing unit and a system interface unit having a plurality of interface ports and a number of transfer networks, each port connected to a different one of said modules and to said transfer networks, wherein said system interface unit controls the transfer of information between said ports, said system further including maintenance apparatus for facilitating diagnosis of failures within any one of said plurality of processing units detected as faulty comprising:

interface means included within the port of each input/output processing unit, said interface means being connected to said clocking circuits;

command register means for storing commands, command decode circuit means, and a plurality of registers included in said system interface unit, said command register means being connected to receive commands from any one of said number of transfer networks, said command decode circuit means connected to said command register means and operative to generate control signals in response to said commands, a first one of said registers being coupled to said interface means of each port for storing coded signals designating different configurations of at least a pair of said plurality of input/output processing units to be enabled for operation, said first register storing signals representative of an unlocked configuration bit pattern designating that only one of said pair is to be enabled and the other one of said pair of disabled for being faulty, said signals conditioning said interface means to inhibit the operation of the clocking circuits to the other one of said pair of input/output processing units having been detected as being faulty; and

,

control circuit means included in each of said input/output processing units, said control circuit means being coupled to said data output means, said clocking circuits and to said interface means,

said command decode circuit means being operative in response to a predetermined sequence of commands from said one of said pair of input/output processing units to generate a sequence of control signals, said interface means of the port of said faulty processing unit in response to said control signals conditioning said control circuit means to enable said data output means to apply the contents of a predetermined one of said number of control registers to the one of said number of transfer networks connected to said port thereby not altering the state of said faulty processing unit defined by the status of said plurality of storage elements, and

said one of said number of transfer networks being conditioned by said control signals to transfer said contents to one of said plurality of registers for use during subsequent fault analysis.

2. The system of claim 1 wherein each of said interfaces includes a plurality of control lines, a first one of said lines being switched to a first state to inhibit said operation of said clocking circuits in response to said coded signals stored in said first register, and

a second one of said lines being connected to said control circuit means, and said second one of said lines being switched to a first state in response to said certain ones of said control signals conditioning said control circuit means to enable said data output means.

3. The system of claim 2 wherein each input/output processing unit further includes a microprogrammed control unit connected to said clocking circuits, said microprogrammed control unit storing sequences of microinstruction words for generating control signals for directing said operation of said input/output processing unit, said first line when switched to said first state inhibiting the operation of said clocking circuits preventing further operation of said microprogrammed control unit and freezing said state of said faulty input/output processing unit, and

said second line when switched to said first state enabling said data output means for readout of said contents of one of said number of control registers without altering said state.

4. The system of claim 3 wherein the microprogrammed control unit of each input/output processing unit includes microinstruction words coded for generating said sequence of said commands.

5. The system of claim 2 wherein said system interface unit further includes a port priority network coupled to each of said ports, said priority network being operative to generate signals indicating which port has the highest priority request, and

transfer control means for controlling the transfer of information between ports, said transfer control means being connected to the transfer networks of each of said input/output processing units, to said port priority network and to said command decode circuit means, said transfer control means in response to said signals from said priority network generating a number of coded signals for selecting one of said transfer networks corresponding to the input/output processing unit which generated a first one of said commands,

said command decode circuit means in response to said number of coded signals switching said second line of the interface of said faulty processing unit to said first state to enable said control circuit means to apply said contents of said one transfer network.

6. The system of claim 5 wherein said command decode circut means includes:

a first register coupled to said transfer control means, said register being conditioned by the signals of said sequence generated in response to a first one of said sequence of commands to store indications of said coded signals specifying which one of said plurality of input/output processing units generated said first one of said commands; and

,

decoder circuit means connected to said first register means, said decoder circuit means being operative in response to said indications to generate signals for switching said second line of said interface of the input/output processing unit of said pair of which did not generate said first one of said commands.

7. The system of claim 6 wherein said command decode means further includes:

a second register connected to said decoder circuit means, said second register being conditioned by signals of said first command from said command register means to store indications of said signals generated by said decoder circuit means, said second register including a plurality of bistable bit positions corresponding in number to said plurality of input/output processing units;

circuit means connecting each bistable bit position to said second line of a different one of said interfaces; and

,

gating means connected to said command register means and to said second register, said gating means being operative in response to a second command in said sequence to cause said transfer control means to condition said contents to said one of said plurality of registers.

8. The system of claim 7 wherein said number of said plurality of input/output processing units includes first and second pairs designated as processing units G, H and E, F and wherein first and second pairs of said plurality of bistable bit positions are assigned to processing units F, E and H, G respectively,

said decoder circuit means including conductor means for connecting different combinations of the outputs of said first register to the set and reset inputs of each of said bistable bit positions for switching one of the bit positions of a pair to a first state identifying said processing unit of said pair which did not generate said first one of said commands.

9. The system of claim 7 wherein said first one of said commands is of a first type coded to specify read out of a predetermined one of said number of control registers of said faulty processing unit and wherein said second one of said commands is of a second type coded to specify loading of a predetermined one of said plurality of registers of said system interface unit with said contents.

10. The system of claim 9 wherein said command decode means further includes reset circuit means connected to said command register means and to said second register means, said reset circuit means being operative in response to the next first type of command to reset said bistable bit positions of said second register means to binary ZEROS.

11. The system of claim 5 wherein said transfer control means includes:

first gating means connected to said command decode means;

second gating means connected to said first gating means and to transfer networks for receiving signals indicating the status; and

,

output gating means connected to said second gating means and to aid port priority network, said output gating means generating a predetermined one of said number of coded signals during a first one of said commands and said output gating means being conditioned by a second one of said commands to complement the state of a predetermined one of said number of coded signals for enabling the transfer of said contents from the transfer network of said faulty processing unit of said pair rather than the processing unit of said pair which generated said first command.

12. The system of claim 11 wherein said first gating means, said second gating means and said output gating means each include NAND gating circuits and wherein aid predetermined one of said number of coded signals corresponds to the least significant bit.

13. The system of claim 11 wherein said output gating means includes:

circuit gating means connected to said port priority network, said circuit gating means generating the remaining ones of said number of coded signals for enabling said transfer network.

14. The system of claim 3 wherein said data output means includes switching means connected to each of said number of control registers and to said control circuit means, and

wherein said control circuit means includes means for generating signals in response to the switching of said second line for selecting the contents of a predetermined one of said number of control registers for application to said one of said number of transfer networks.

15. A data processing system including a plurality of modules, said plurality of modules including at least a pair of input/output processing units, each processing unit including a plurality of storage elements including at least one control register for storing status and control information required for program processing and timing circuits for generating signals for enabling said processing unit and a system interface unit having a plurality of interface ports and a number of transfer networks, each port being connected to a differnt one of said modules and to said transfer networks wherein said system interface unit controls the transfer of information between said ports, said system further including maintenance apparatus for facilitating the diagnosis of faults within an inactive processing unit comprising:

interface means included within the port of each input/output processing unit, said interface means being connected to said timing circuits;

command register means for storing commands, command decode circuit means, and a plurality of registers included in said system interface unit, said command register means being connected to receive commands from any one of said number of transfer networks, said command decode circuit means connected to said command register means and operative to generate control siganls in response to said commands, a first one of said registers being coupled to said interface means of each port and for storing coded signals designating different configurations of said air of input/output processing units enabled for operation, said first register storing signals representative of an unlocked configuration bit pattern designating that only one of said pair is to be enabled for operation, said interface means being conditioned by said bit pattern to inhibit the operation of the timing circuits of the other one of said pair of input/output processing units rendering it inactive; and

,

control circuit means included in each of said input/output processing units, said control circuit means being coupled to said timing circuits and to said interface means,

said command decode circuit means being operative in response to a first predetermined type of command from said one processing unit of said pair of input/output processing units to generate a first sequence of control signals, said interface means of said inactive processing unit being operative in response to said control signals to condition said control circuit means to apply the contents of said one control register to one of said number of transfer networks for use during fault analysis thereby not altering the state of said inactive processing unit defined by the status of said plurality of storage elements.

16. The system of claim 15 wherein said apparatus further includes transfer control means connected to the transfer networks of each of said processing units for controlling the transfer of information between ports, said command decode circuit means being operative in response to a second predetermined type of command from said one processing unit to a second sequence of control signals, said transfer control means being conditioned by said control signals to transfer said contents from said one transfer network to one of said plurality of registers of said system interface unit.

17. The system of claim 15 wherein each processing unit further includes data output means operatively coupled to said control register and each of said interfaces including a plurality of control lines, a first one of said lines being switched to a first state to inhibit said operation of said clocking circuits in response to said coded signals stored in said first register, and

a second one of said lines being connected to said control circuit means, said second one of said lines being switched to a first state in response to said certain ones of said control signals conditioning said control circuit means to enable said data output means for readout of said contents without altering said state.

18. The system of claim 17 wherein each input/output processing unit further includes a microprogrammed control unit connected to said clocking circuits, said microprogrammed control unit storing sequences of microinstruction words for generating control signals for directing said operation of said input/output processing unit, said first line when switched to said first state inhibiting the operation of said clocking circuits preventing further operation of said microprogrammed control unit and freezing said state of said inactive input/output processing unit, and

said second line when switched to said first state enabling said data output means for readout of said contents of said one control register without altering said state.

19. The system of claim 18 wherein said system interface unit further includes a port priority network coupled to each of said ports, said priority network being operative to generate signals indicating which port has the highest priority request, and

said transfer control means being connected to said port priority network and to said command decode circuit means, said transfer control means in response to said signals from said priority network generating a number of coded signals for selecting one of said transfer networks corresponding to the input/output processing unit which generated said first command,

said command decode circuit means in response to said number of coded signals switching said second line of the interface of said inactive processing unit to said first state to enable said control circuit means to apply said contents from said data output means to said one transfer network.

20. The system of claim 19 wherein said command decode circuit means includes:

a first register coupled to said transfer control means, said first register being conditioned by the signals of said sequence generated in response to said first command to store indications of said coded signals specifying which one of said plurality of input/output processing units generated said first command; and

,

decoder circuit means connected to said first register means, said decoder circuit means being operative in response to said indications to generate signals for switching said second line of said interface of the input/output processing unit of said pair which did not generate said first command.

21. The system of claim 20 wherein said command decode means further includes:

a second register connected to said decoder circuit means, said second register being conditioned by signals of said first command from said command register means to store indications of said signals generated by, said decoder circuit means, said register means including a plurality of bistable bit positions corresponding in number to said pair of input/output processing units; and

,

circuit means connecting said bistable bit position to said second line of a different one of said interfaces,

gating means connected to said command register means and to said second register, said gating means being operative in response to a second command to cause said transfer control means to condition said one of said number of transfer networks to transfer said contents to said one of said plurality of registers.

22. The system of claim 21 wherein said transfer control means includes:

first gating means connected to said command decode means;

second gating means connected to said first gating means and to transfer networks for receiving signals indicating the status; and

,

output gating means connected to said second gating means and to said port priority network, said output gating means generating a predetermined one of said number of coded signals during said first command and said output gating means being conditioned by said second command to complement the state of a predetermined one of said number of coded signals for enabling the transfer of said contents from the transfer network of said inactive processing unit of said pair rather than the processing unit of said pair which generated said first command.

23. A data processing system comprising:

a plurality of modules, said plurality of modules including a plurality of input/output processing units, each processing unit including;

a number of control register for storing status and control information required for program processing;

data output means connected to said number of control registers for selection of any one of said number of registers;

timing circuits for enabling the operation of said processing unit;

interface means for transferring data and control signals to and from said processing unit, said interface means being connected to said timing circuits and to said control circuit means, and

control circuit means coupled to said data output means, said timing circuits and to said interface means, and

a system interface unit for controlling the transfer of information between said plurality of modules, said system interface unit including;

a plurality of interface ports, each connected to a different one of said modules;

a number of transfer networks connected to a different one of said plurality of input/output processing units;

command register means, said command register means being connected to receive commands from said number of transfer networks;

command decode circuit means coupled to said command register means, said command decode circuit means being operative to generate control signals in response to said commands, and

a plurality of registers, a first one of said registers coupled to said interface means of each port and storing bit pattern signals codes for designating different operating configurations of pairs of said plurality of input/output processing units defining which processing units of said pairs are to be enabled for operation, said first register storing signals corresponding to a predetermined configuration, said signals conditioning said interface means to inhibit the operation of the timing circuits of a designated one processing unit of one of said pairs of input/output processing units rendering it inactive, and

said command decode circuit means being operative in response to a first type of command from the other one of said one pair to generate a sequence of control signals, said interface means of the inactive processing unit in response to said control signals conditioning said control circuit means to cause said data output means to apply the contents of a selected one of said number of control registers for subsequent examination for diagnosis of faults within said inactive processing unit to one of said number of transfer networks thereby not altering the state of said inactive processing unit defined by the contents of said number of control registers.

24. The system of claim 23 wherein said system interface unit further includes transfer control means connected to the transfer networks of each of said processing units for controlling the transfer of information between ports, said command decode circuit means being operative in response to a second predetermined type of command from said other processing unit to a second sequence of control signals, said transfer control means being conditioned by said control signals to transfer said contents from said one transfer network to one of said plurality of registers of said system interface unit.

25. The system of claim 24 wherein each of said interfaces includes a plurality of control lines, a first one of said lines being switched to a first state to inhibit said operation of said clocking circuits in response to said coded signals stored in said first register, and

a second one of said lines being connected to said control circuit means, said second one of said lines being switched to a first state in response to said control signals conditioning said control circuit means to enable said data output means for readout of said contents.

26. The system of claim 25 wherein each input/output processing unit further includes a microprogrammed control unit connected to said clocking circuits, said microprogrammed control unit storing sequences of microinstruction words for generating control signals for directing said operation for said input/output processing unit, said first line when switched to said first state inhibiting the operation of said clocking circuits preventing further operation of said microprogrammed control unit and freezing said state of said inactive input/output processing unit, and

said second line when switched to said first state enabling said data output means for readout of said contents of one of said number of registers without altering said state.

27. The system of claim 25 wherein said system interface unit further includes a port priority network coupled to each of said ports, said priority network being operative to generate signals indicating which port has the highest priority request, and wherein

said transfer control means is connected to said port priority network and to said command decode circuit means, said transfer control means in response to said signals from said priority network generating a number of coded signals for selecting one of said transfer networks corresponding to the input/output processing unit which generated said first command,

said command decode circuit means in response to said number of coded signals switching said second line of the interface of said inactive processing unit to said first state to enable said control circuit means to apply said contents to said one transfer network.

28. The system of claim 27 wherein said command decode circuit means includes:

a first register coupled to said transfer control means, said first register being conditioned by the signals of said sequence generated in response to said first command to store indications of said coded signals specifying which one of said plurality of input/output processing units generated said first command; and

,

decoder circuit means connected to said first register means, said decoder circuit means being operative in response to said indications to generate signals for switching said second line of said interface of the processing unit of said pair which did not generate said first command.

29. The system of claim 28 wherein said command decode means further includes:

a second register connected to said decoder circuit means, said second register being conditioned by signals of said first command from said command register means to store indications of said signals generated by said decoder circuit means, said register means including a plurality of bistable bit positions corresponding in number to said plurality of input/output processing units;

circuit means connecting each bistable bit position to said second line of a different one of said interfaces; and

,

gating means connected to said command register means and to said second register, said gating means being operative in response to a second command in said sequence to cause said transfer control means to condition the transfer networks of said pair of processing units for enabling the transfer of said contents to said one of said plurality of registers.

30. The system of claim 29 wherein said transfer control means includes:

first gating means connected to said command decode means;

second gating means connected to said first gating means and to transfer networks; and

,

output gating means connected to said second gating means and to said port priority network, said output gating means generating a predetermined one of said number of coded signals during a first one of said commands and said output gating means being conditioned by said second command to complement the state of a predetermined one of said number of coded signals for conditioning said transfer networks to enable the transfer of signals from the transfer network of said inactive processing unit of said pair rather than the transfer network of processing unit of said pair which generated said first command.