Information storage facility with multiple level processors

• US 4,096,567 A
• Filed: 08/13/1976
• Issued: 06/20/1978
• Est. Priority Date: 08/13/1976
• Status: Expired due to Term

• Current Assignee: Allan J. Killian, Bruce A Van Natta, William H. Millard
• Original Assignee: Allan J. Killian, Bruce A Van Natta, William H. Millard
• Inventors: Millard, William H., Van Natta, Bruce A., Killian, Allan J.
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/714,212
• Time in Patent Office: 676 Days
• Field of Search: 340/172.5, 364/200 MS File
• US Class Current: 1/1
• CPC Class Codes: G06F 16/221 Column-oriented storage; Management thereof

Abstract

An information storage facility with multiple level processors for relieving one or more external host computers or intelligent terminals from conventional time consuming record searching functions, such as record formatting, indexing, buffering and the like. Three processor levels are provided: a communications level for handling external communications, a DBMS level for performing syntax scanning, hashing and coding/decoding routines, and data access functions e.g. indexing, searching, buffering, blocking, deblocking, storage management, and error recovery functions; and a storage level for performing data storage and retrieval, error recovery and storage device management.

A direct memory access bus is also provided which enables high speed data transfer among the several processors included within the storage facility and also external host computers or intelligent terminals.

Claims

1. A multi-level information storage facility for storing data base information in digital form and for enabling symbolic access to such information in response to information request signals from an external processing device, said facility comprising:

a communications level processor means having an input/output port means for receiving said information request signals from said external processing device, said communications level processor means including means for initiating internal processing of said request signals and means for generating acknowledgment signals for transmission to said external processing device via said input/output port means;

an intermediate level processor means for providing intermediate level processing of said request signals;

first shared memory means coupled to said communications level and said intermediate level processor means for enabling data communication therebetween, said first shared memory means including a first cache memory device for storing initiating request signals generated by said communications level processor means and for storing resultant task signals generated by said intermediate level processor means;

said intermediate level processor means including seek means for interrogating said first cache memory device in a predetermined sequence for said initiating request signals, means for generating intermediate level instruction signals in response to the detection of said initiating request signals, and means for storing said resultant task signals in said first cache memory device;

storage level processor means having an input/output port means adapted to be coupled to a data storage device for controlling operation thereof; and

second shared memory means coupled to said intermediate level and said storage level processor means for enabling data communication therebetween, said second shared memory means including a second cache memory device for storing said intermediate level instruction signals from said intermediate level processor means and for storing data received from said storage level processor means;

said storage level processor means including means for interrogating said second cache memory device for said intermediate level instruction signals, means for generating storage level instruction signals in response to the detection of said intermediate level instruction signals for controlling storage and retrieval of portions of said data base information from said storage device, and means for storing said data received from said storage device in said second cache memory device.

2. The combination of claim 1 wherein said communications level processor means includes a plurality of processor units each having input/output port means adapted to be coupled to a plurality of external processing devices.

3. The combination of claim 1 wherein said intermediate level processor means comprises a plurality of processor units coupled to said first shared memory means in parallel for data communication with said first processor means.

4. The combination of claim 1 wherein said storage level processor means includes a plurality of processor units each having input/output port means adapted to be coupled to a separate data storage device for controlling operation thereof.

5. The combination of claim 1 wherein said data storage device comprises a disk storage unit.

6. The combination of claim 1 further including a direct memory access bus coupled to said communications level, intermediate level and storage level processor means and adapted to be coupled to said external processing device for providing a high speed data transfer therebetween.

7. The combination of claim 6 wherein said direct memory access bus includes additional processor means for controlling the operation thereof.

8. The combination of claim 1 wherein said first and second cache memory devices each comprises an expandable cache memory.