Offset compensating circuit

• US 4,097,860 A
• Filed: 02/09/1977
• Issued: 06/27/1978
• Est. Priority Date: 02/10/1976
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Ochiai, Kazuo, Maruta, Rikio, Araseki, Takashi
• Primary Examiner(s): Smith, Jerry
• Application Number:
  US05/766,848
• Time in Patent Office: 503 Days
• Field of Search: 235/152, 235/164, 340/347 CC, 307/354, 307/356, 307/359, 307/362, 328/149, 328/150, 328/165, 328/167
• US Class Current: 341/118
• CPC Class Codes: H03M 1/1295 Clamping, i.e. adjusting the DC level of the input signal to a predetermined value

Abstract

Method and apparatus for cancelling a deviation in an input signal due to drift, line or background noise, changes in circuit component characteristics due to aging, and the like wherein the input signal, typically a digitized representation of an analog signal, is altered by a presumed offset magnitude; the polarity of the difference is monitored and a negative or positive count of clock pulses is accumulated dependent upon the aforesaid polarity. When a determined positive (or negative) count is reached the presumed offset is adjusted (up or down) by a predetermined increment and the count is begun anew.

As an alternative technique and embodiment the initiation of the count may be restrained as long as the magnitude of the digitized input signal exceeds a predetermined threshold.

Claims

1. An offset compensating circuit comprising:

a subtractor for subtracting a presumed value of the offset from the input signal to form the output signal;

a sign decision circuit for determining an algebraic sign of the output signal of said subtractor circuit;

a clock pulse source;

a bidirectional counter for counting pulses from said source having its count-up and count-down function controlled by the output signal of said sign decision circuit and adapted to produce respective output signals when it has overflowed in an increasing direction and in a decreasing direction; and

an offset setting circuit in which an internal setting value representing the presumed value of the offset is increased upon overflow of said counter in the increasing direction while said internal setting value is decreased upon overflow of said counter in the decreasing direction.

2. The apparatus of claim 1 wherein said counter includes means for clearing the contents therein whenever the counter overflows in either the increasing or decreasing direction.

3. The apparatus of claim 1 further comprising means for limiting the absolute magnitude of the offset signal regardless of the receipt of further outputs from the counter.

4. An offset compensating circuit comprising:

a subtractor for subtracting a presumed value of the offset from the input signal to form the output signal;

a sign decision circuit for determining an algebraic sign of the output signal of said subtractor circuit;

a clock pulse source, a bidirectional counter for counting pulses from said source and having its count-up and count-down function controlled by the output signal of said sign decision circuit and adapted to produce respective output signals when it has overflowed in either an increasing direction or in a decreasing direction;

an offset setting circuit in which an internal setting value representing the presumed value of the offset is increased upon overflow of said counter in the increasing direction while said internal setting value is decreased upon overflow of said counter in the decreasing direction; and

a threshold circuit for inhibiting the increasing and decreasing variations of said counter when the output value of said subtractor exceeds a predetermined value.

5. The apparatus of claim 4 wherein said counter includes means for clearing the contents therein whenever the counter overflows in either the increasing or decreasing direction.

6. The apparatus of claim 4 further comprising means for limiting the absolute magnitude of the offset signal regardless of the receipt of further outputs from the counter.

7. A method for substantially cancelling certain components within an input signal, which components contribute to a deviation from the true value which the input signal should represent comprising:

selecting an arbitrary offset value;

subtracting the offset value from the input signal;

detecting the polarity of the resulting difference signal;

counting at a predetermined rate and in a direction (positive or negative) dependent upon the polarity of the difference signal;

altering the magnitude of the present offset value by a predetermined positive or negative increment when the aforesaid count respectively reaches either a predetermined positive or negative magnitude.

8. The method of claim 7 further comprising the steps of monitoring the input signal and restraining the counting operation whenever the input signal is above (or below) a predetermined positive (or negative) magnitude.

9. The method of claim 7 further comprising the step of limiting the absolute magnitude of the offset signal regardless of the fact that additional alterations are requested due to said count reaching said predetermined magnitude.