Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle

• US 4,099,231 A
• Filed: 10/01/1975
• Issued: 07/04/1978
• Est. Priority Date: 10/01/1975
• Status: Expired due to Term

• Current Assignee: Digital Equipment Corporation (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Guglielmi, Paul M., Sullivan, Patrick, Kotok, Alan, Gross, David A.
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/618,604
• Time in Patent Office: 1,007 Days
• Field of Search: 340/172.5, 364/200 MS File, 364/900 MS File
• US Class Current: 711/168
• CPC Class Codes: G06F 13/1647 with interleaved bank access

Abstract

A memory control apparatus for use in a digital computer system. The computer system comprises a central processing unit and a main memory which has a plurality of memory units. The processor has control circuitry for simultaneously addressing a plurality of words stored in the memory locations in the memory units. The processor addresses the plurality of words by the combination of a memory address signal and word request control signal which are equal to the number of words to be transferred. While addressing of the memory units occurs in parallel, the transfer of words occurs serially. The initial word as defined by the memory address signal is transferred first with the remaining words transferred in ascending modulo four order. If one or more of the four words has not been requested, it is automatically skipped by the control apparatus with no loss in time or continuity. Logic in both the processor and the memory unit is initialized to acount for the words being transferred such that each word selected is stored in the proper buffer.

Claims

1. In a data processing system of the type including a central processing unit for addressing memory locations in a plurality of memory units, each of said memory units storing data in said memory locations, each memory location having a unique address, and bus means connecting the central processing unit and the memory units for transmission of data, memory address and control signals, an apparatus for controlling in a memory cycle the transfer of data between said processing unit and said memory units, said apparatus comprising:

A. first means coupled to said central processing unit and responsive to a memory start signal and a plurality of word request control signals from said central processing unit for simultaneously generating a plurality of memory request signals to said memory units, via said bus means, each of said memory request signals in conjunction with said memory address signals identifying one of said memory locations in said memory units;

B. second means coupled to said central processing unit and responsive to said memory address signals, said word request control signals and said memory start signal for storing identifiers of the order of the addressed memory location from which data is to be transferred;

C. third means coupled to said central processing unit and responsive to said word request control signals for storing a plurality of first signals equal to the number of said memory request signals transferred over said bus means to said memory units, said third means coupled to said memory start signal for disabling said memory start signal; and

D. fourth means coupled to said memory units and responsive to said first means for serially identifying to said central processing unit and transferring between said central processing unit and said memory units the data stored in each of said memory locations responsive to the combination of said memory address signals and said memory request signals.

2. An apparatus as defined in claim 1 wherein said fourth means include:

A. means responsive to said memory address signals for identifying the initial memory location in said memory units with which the data is to be transferred;

B. means responsive to said memory request signals and said identifying means for altering said identifying means to identify the next memory location in said memory units with which data is to be transferred;

C. means responsive to said identifying means and said memory start signal for generating a plurality of first and second control signals to said third and said second means, respectively, each of said first and second control signals indicating the status of said memory units.

3. An apparatus as defined in claim 2 wherein said third means include:

A. acknowledge means responsive to said first control signals from said memory units for comparing the number of said first control signals from said memory units to the number of said memory request signals from said first means, said acknolwedge means upon said comparison indicating that the total number of acknowledge signals equal the total number of memory request signals disabling said memory start signal.

4. An apparatus as defined in claim 3 wherein said second means further includes:

A. valid means responsive to said second control signals from said memory units indicating that said memory units have exchanged data in said memory locations, said valid means, upon receiving a number of second control signals from said memory units equal to the number of said plurality of memory request signals from said first means, disabling said memory cycle.

5. An apparatus as defined in claim 4 wherein said third means further includes control means responsive to said second means for initializing said valid means such that said plurality of first signals is rotated to indicate the order with which data is to be transferred between said memory units and said processing unit.

6. An apparatus as defined in claim 5 and further including data buffer means coupled to said central processing unit for storing data and, wherein said valid means shifts the order of said first signals in response to said second control signals, said valid means identifying one of said data buffer means for storing the data to be transferred between said processing unit and said memory units.

7. An apparatus as defined in claim 6 and further including:

A. fifth means coupled to said acknowledge means for accounting for the absence of at least one of said plurality of first signals from said first means, said fifth means in response to each of said first control signals accounting for one of said first signals, said fifth means in response to the absence of at least one of said first signals automatically shifting said acknowledge means such that said absence of one of said first signals is accounted for.

8. An apparatus as defined in claim 7 and further including:

A. sixth means coupled to said valid means for accounting for the absence of a request from said first means;

B. said valid means selectively correlating the order in which the data between said central processing unit and said memory units is exchanged such that said date in said central processing unit is properly accounted for;

C. said sixth means in response to each of said second control signals from said memory units accounting for one of said memory request signals from said first means; and

D. said sixth means in response to the absence of said memory request signals automatically shifting said valid means.

9. An apparatus as defined in claim 8 wherein said acknowledge means includes a shift register for shifting the order of said first signals and said valid means includes a shift register for rotating and shifting the order of said plurality of first signals.

10. An apparatus as defined in claim 2 wherein said generating means include:

A. data acknowledge means for generating said first control signals indicating that said memory units contain said memory locations; and

B. data valid means for generating said second control signals indicating that the data in said memory locations has been transferred over said bus means between said central processing unit and said memory units.

11. An apparatus as defined in claim 10 wherein said data acknowledge means include:

A. seventh means responsive to said first means and to said memory start signal for generating to said central processing unit the initial one of said first control signals upon receipt of said memory start signal; and

B. eighth means responsive to said seventh means and to a memory enable signal from said memory units for generating subsequent first control signals to said central processing unit.

12. An apparatus as defined in claim 2 wherein said fourth means include:

A. at least two memory controllers, each controller responsive to said plurality of memory request signals from said first means;

B. a plurality of storage modules, the even numbered storage modules coupled to at least one of said memory controllers and the odd numbered storage modules coupled to at least the other of said memory controllers; and

C. means coupled to said memory controllers and responsive to the combination of said memory address signals and said memory request signals for generating a code indicating each of the memory locations with which the data is to be transferred.

13. An apparatus as defined in claim 12 wherein:

A. said one memory controller having said even storage modules provides said first and second control signals to said central processing unit when said data to be transferred is from said even storage modules, said one memory controller being inhibited when said data to be transferred is from said odd storage modules; and

B. said other memory controller having said odd storage modules provides said first and second control signals to said central processing unit when said data to be transferred is from said odd storage modules, said other memory controller being inhibited when said data to be transferred is from said even storage modules.

14. In a data processing system of the type including a central processing unit for addressing memory locations in a plurality of memory units, each of said memory units storing data in said memory locations, each memory location having a unique address, and bus means connecting the central processing units and memory units for transmission of data, memory addresses and control signals, an apparatus for controlling in a memory cycle the trnasfer of data between said processing unit and said memory units, said apparatus comprising:

A. means responsive to a memory start signal from said processing unit for simultaneously addressing in said memory units a variable number of memory locations with which data is to be transferred;

B. means within said memory units for serially responding to said simultaneously addressing means, said responding means including;

16. An apparatus as defined in claim 14 wherein said second ordering means include:

A. means responsive to said simultaneously addressing means for storing word request signals corresponding to the total number of addressed memory locations;

B. means responsive to said first plurality of control signals for shifting said storing means to indicate the acknowledgement of data in one of said memory locations; and

C. means coupled to said storing means and responsive to the absence of said word request signals for automatically shifting said storing means so as to identify the next data exchange in said central processing unit to correlate with the next transfer with said memory units.

17. An apparatus as defined in claim 14 wherein said simultaneously addressing means include the combination of:

A. said memory address signal addressing one of said memory locations in said memory units; and

memory address signal having a first part and a second part, said first part capable of addressing a number of said memory locations and said second part identifying one of said memory locations;

B. a plurality of word request signals indicating the total number of words to be serially accessed by said memory unit, said first part of said memory address signal and each of said word request signals identifying each of said memory locations; and

wherein,

C. said second ordering means in response to said second part of said memory address signal and said word request signals is arranged to account for each data transfer in modulo four order; and

whereby, said combination of said memory address signal and said word request signals address a variable number of memory locations in said memory units.

20. The system as defined in claim 17 wherein said second means includes:

A. means responsive to clock pulses in said central processing unit for decrementing the value of said second part of said memory address signal; and

B. means for inhibiting said decrementing means when said vaue becomes zero.

23. An apparatus as defined in claim 17 wherein said third means is shifted in response to a second set of control signals from said seventh means, said third means compares the number of said word request signals to the number of said second set of control signals, and wherein said third means further includes:

A. means responsive to the absence of a word request control signal for automatically shifting said third means; and

B. means responsive to the absence of a predetermined number of word request signals for terminating said memory start signal.

15. first means for ordering the accessing of said variable number of memory locations in said memory units;

and

2. means responsive to said first ordering means for generating a first and second plurality of control signals equal in number to the number of simultaneously addressed memory locations; and

C. means within said central processing unit and responsive to said serially responding means for correlating the data transferred between said central processing unit and said memory units, said correlating means including;

1. second means for ordering in said central processing unit the transfer of data between said variable number of memory locations and said central processing unit; and

2. means responsive to said second plurality of control signals for changing said second ordering means, said second ordering means identifying to said central processing unit each serial exchange of said data.

18. A data processing system for accounting for transfer of words between a central processing unit and a plurality of memory units over a bus means, said central processing unit addressing a plurality of memory locations in said memory units in parallel and wherein the transfer of words between said central processing unit and said memory units occurs in series, said system comprising:

A. first control means in said central processing unit comprising;

1. first means responsive to a memory start signal and word request control signals for providing memory request signals to said memory units;

2. second means responsive to said memory start signal and to a first part of said memory address signal for identifying an initial word to be transferred;

3. third means responsive to said word request control signals for storing said word request control signals, said third means identifying the total number of words requested by said central processing unit; and

21. A system as defined in claim 18 wherein:

A. said fourth means in response to said decrementing means of said second means rotates said order of words to be exchanged such that said order in said fourth means corresponds to the order said words are transferred to said memory units; and

B. wherein said fourth means further includes;

1. means responsive to the absence of word request control signals in said fourth means for automatically rotating said order of words such that the absence of word request control signals is not acknowledged.

19. fourth means responsive to said word request control signals and to said second means for storing said word request control signals, said fourth means identifying the order of said words to be exchanged between said central processing unit and said memory units;

and

B. second control means in said memory units comprising;

1. fifth means responsive to said first part of said memory address signal for identifying in said memory units the initial word to be transferred;

2. sixth means responsive to said fifth means and said memory request signals for enabling said fifth means to identify the next word in said memory units to be trnsferred; and

3. seventh means responsive to said memory request signal and a memory enable signal for providing a plurality of control signals indicating the status of said memory units to said central processing unit.

22. An apparatus as defined in claim 19 wherein said fourth means further includes:

A. means responsive to one set of control signals from said seventh means for rotating said order of words in said fourth means;

such that said fourth means compares said word request signals to said one set of control signals;

B. said rotating means including means for altering during the rotation the lowest order word such that it indicates the absence of a word request signal; and

C. means responsive to the absence of a predetermined number of word request control signals in said fourth means for indicating the completion of transfers between said central processing unit and said memory units.