Class B FET amplifier circuit

• US 4,100,502 A
• Filed: 08/31/1976
• Issued: 07/11/1978
• Est. Priority Date: 09/03/1975
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamashiro, Osamu
• Primary Examiner(s): Kominski, John
• Application Number:
  US05/719,238
• Time in Patent Office: 679 Days
• Field of Search: 331/116 R, 331/114, 330/13, 330/35, 330/15, 330/38 M, 330/263, 330/264, 330/269, 330/277, 58/23
• US Class Current: 330/264
• CPC Class Codes: G04F 5/06 using piezoelectric resonators
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, the gate of the two FETs being applied with a common linear input, respective load resistors connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs, and a bias resistor connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.

Claims

1. An FET circuit comprising an amplifier stage and a waveform shaping stage;

said amplifier stage including a first p-channel FET and a first n-channel FET, means for biasing the gate of each of said FETs at a dc level nearly equal to its drain potential, (means for setting the potential differential between the source and the drain of each of said FETS at a voltage nearly equal to its threshold voltage;

) and means for supplying a linear input signal to said gates through respective capacitors; and

said waveform shaping stage comprising means for converting a linear signal into a digital signal including a second p-channel FET having a gate coupled to the drain of said first p-channel FET, and a second n-channel FET having a gate coupled to the drain of said first n-channel FET.

2. An amplifier circuit comprising a complementary inverter including a first FET of a first conductivity type connected to a first source potential, a second FET of a second conductivity type connected to a second source potential, and an input terminal connected to the gates of said first and second FETs, the circuit comprising:

a series connection of first and second load resistors connected between said first and second FETs;

a respective bias resistor connected between the gate and the drain of each of said first and second FETs;

a respective capacitor connected between the input terminal and the gate of each of said FETs; and

output means connected to the drains of said FETs.

3. The amplifier circuit according to claim 2, in which said output means comprises a terminal connected to the interconnection point of said load resistors.

4. The amplifier circuit according to claim 2, in which said output means comprises a pair of terminals connected to the drains of said first and second FETs, respectively.

5. An amplifier circuit comprising, in combination,

first and second operating voltage terminals of different potential level;

first and second field effect transistors (FET) of complementary conductivity type, each having a source, a gate and a drain, the sources of said complementary FETs being connected to said first and second operating voltage terminals respectively, the gates of said complementary FETs being ac-coupled to an input terminal; and

a resistor connected between the drains of said complementary FETs, the connection between said resistor and said complementary FETs serving as an output terminal.

6. The amplifier circuit according to claim 5, further comprising a biasing resistor connected between the gate and the drain of at least one of said first and second FETs, the bias potential between the gate and the source of said FET being determined at a potential nearly equal to its threshold voltage.

7. The amplifier circuit according to claim 5, further comprising a first and a second biasing resistors connected between the gates and the drains of said first and second FETs respectively, and an ac coupling capacitor connected between the gate of said first FET and said input terminal, the input terminal being connected directly to the gate of said second FET.

8. A complementary push-pull amplifier comprising:

a p-channel FET having a source coupled to a positive power source terminal, a gate and a drain;

an n-channel FET having a source coupled to a negative power source terminal, a gate and a drain;

resistive means coupled between said drains of said FETs and;

means for applying an a.c. input signal to said gates of said FETs to operate said FETs in a push-pull mode.

9. The amplifier as defined in claim 8 further including means for applying to the gate of one of said FETs a bias voltage substantially equal to its drain d.c. potential.

10. The amplifier as defined claim 9 further including means for applying to the gate of the other FET a bias voltage substantially equal to its drain d.c. potential, and a d.c. blocking capacitor coupled between said gates of said FETs.

11. A complementary push-pull comprising a p-channel FET, an n-channel FET, resistive load means connected to at least one of said FETs, a resistive bias means coupled between the gate and drain of said one FET for applying a bias voltage substantially equal to the drain d.c. potential of said FET to said gate thereof, means for connecting said FETs and said resistive load means so that said resistive load means and the conduction paths between the sources and the drains of the respective FETs are connected in series and, means for applying an a.c. input signal to the gates of said FETs, the resistance of said load means being higher than the on-resistance of said one FET and the potential differential between the source and gate of said one FET approaching its threshold voltage.

12. The amplifier as defined in claim 11 comprising a d.c. blocking capacitor coupled between the gates of said FETs, resistive bias means coupled between the gate and drain of the other FET of applying a bias voltage substantially equal to the drain d.c. potential of the other FET to the gate thereof and, output deriving means wherein said load means is coupled between the drains of both FETs so as to act as a common load for both FETs, the resistance of said load means being higher than the on-resistance of the other FET and the potential differential between the source and gate of the other FET approaching its threshold voltage, said output deriving means deriving at least one output from the node between the drains of both FETs.

13. The amplifier as defined in claim 12 in which a single capacitor is connected between the gates of both FETs, said a.c. input signal being directly applied to the gate of one of said FETs and being applied to the gate of the other by way of said single capacitor.

14. A complementary FET circuit comprising an amplifier stage and a succeeding state, each being comprised of complementary FETs, said amplifier stage including means for producing two output signals having d.c. potentials different from each other in response to an input signal, said succeeding stage having two input terminals for receiving said two output signals.

15. The FET circuit as defined in claim 14, in which each of said stages comprises a p-channel FET and an n-channel FET, the respective potential differential between the source and the drain of each FET in said amplifier stage is supplied between the source and the gate of the corresponding FET in said succeeding stage, respectively, and said respective potential differential is substantially equal to the threshold voltage of that FET.