High speed manchester encoder

• US 4,100,541 A
• Filed: 07/26/1976
• Issued: 07/11/1978
• Est. Priority Date: 07/26/1976
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Quesnell, Harris A. Jr.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US05/708,779
• Time in Patent Office: 715 Days
• Field of Search: 340/347 DD, 360/42, 178/67, 178/66 R
• US Class Current: 341/70
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

High speed manchester encoding is provided by latching input data by meansf a first clock pulse to provide a synchronized data source. This synchronized data is latched and inverted in a second latch circuit by a second clock pulse 180° out of phase with the first clock pulse. The synchronized and inverted data is fed to a multiplexer where either data or data is selected depending on the state of the master clock applied to the select input of the multiplexer. The output from the multiplexer is the manchester encoded data stream.

Claims

1. A high speed manchester encode comprising:

(a) input means for receiving serial data,

(b) synchronizing means coupled to said input means for providing a first data stream and a second delayed and inverted data stream,

(c) a multiplexer coupled to said synchronizing means for selecting either of said data streams to provide a manchester encoded data stream output.

2. The encoder of claim 1 wherein said synchronizing means includes a first latch circuit coupled to said input means and being latched by a first clock source and a second latch circuit coupled to said first latch circuit and being latched by a second clock source 180°

out of phase with the first clock source.

3. The encoder of claim 2 wherein said first and second clock sources are generated from a master clock source.

4. The encoder of claim 3 wherein said multiplexer is of the time dimension type and responds to a logic zero to select said first data stream and responds to a logic one to select said second data stream.

5. A high speed manchester encoder comprising:

(a) a source of serial data,

(b) latch circuit means for converting said serial data to a first data stream synchronized with a first clock source and a second data stream that is inverted and synchronized with a second inverted clock source,

(c) a multiplexer coupled to said latch circuit means for selecting either of said data streams determined by the state of the clock source applied to the select input.

6. The encoder of claim 5 wherein said latch circuit means includes:

(a) a first D latch circuit having a first input coupled to said data source, a second input coupled to the first clock source and having an output,

(b) a second D latch circuit having a first input coupled to the output of said first D latch circuit, a second input coupled to the inverted clock source and having an output.

7. The encoder of claim 6 wherein the select clock source of said multiplexer is of the same frequency as said first and second clock sources.

8. A high speed manchester encoder comprising:

(a) a source of input serial data,

(b) a master clock source,

(c) a clock pulse generator coupled to said master clock source for generating two clocks 180°

out of phase with each other,

(d) a first D latch circuit having a first input coupled to said data source, a second input coupled to one of said clocks and having an output,

(e) a second D latch circuit having a first input coupled to the output of said first D latch circuit, a second input coupled to the other of said clocks and having an inverted output,

(f) a multiplexer having a first input coupled to the output of said first D circuit, a second input coupled to the inverted output of said second D latch circuit, a select input coupled to said master clock source and having an output.