Error status reporting

• US 4,100,605 A
• Filed: 11/26/1976
• Issued: 07/11/1978
• Est. Priority Date: 11/26/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Holman, Bruce James
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/745,512
• Time in Patent Office: 592 Days
• Field of Search: 364/900 MS File, 235/153 AK, 340/173 R, 340/174 MC, 307/221 R, 328/37
• US Class Current: 714/25
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A plurality of status reporting units are connected respectively to a plurality of shift registers. The shift registers receive and store status signals from the status reporting units. Each of the shift registers include an OR circuit for combining the signals from all of the stages of the respective shift registers. An output of the OR circuit is connected to the input of one stage of a shift register other than the shift register supplying signals thereto. The arrangement is such that the one stage in the respective shift registers indicate the status of one or more error status reporting units. A status analyzing unit receives signals from the various shift registers for analyzing error patterns of the status reporting units in response to receiving a signal that at least one of the status reporting units has error status to report.

Claims

1. A digital signal propagation unit, including in combination,

a first plurality of shift registers, each said shift register having a plurality of settable shift register stages, and being interconnected as a single string of serially connected shift registers, and

a plurality less than said first plurality of OR circuits respectively receiving signals from stages of predetermined ones of said plurality of shift registers and each said OR circuits each having an output connected to one of said shift register stages in other than those shift registers from which signals are received by such OR circuit.

2. The unit set forth in claim 1 further including in combination, less than all of said stages in at least one of said shift registers being connected to a respective one of said OR circuits.

3. The unit set forth in claim 1 further including means to simultaneously shift all signals in all of said shift registers, and

means in each of said shift registers for independently receiving signals for storage therein.

4. A data processing system having a status reporting unit including in combination,

a status analyzing unit for receiving status,

a plurality of status reporting units for supplying status signals, some of said status signals being error indicating signals,

a like plurality of registers, each having a plurality of stages, respectively connected to said status reporting units for receiving said status signals,

a like plurality of OR circuits, respectively connected to said registers, having inputs from predetermined ones of said stages of said respective registers and having an output,

each of said plurality of registers less one having a stage for receiving signals from the output of said respective OR circuits less one, and

one of said OR circuits being connected to said status analyzing unit for supplying an alert signal thereto.

5. The data processing system set forth in claim 4 further including a signal transfer line extending from said status analyzing units to said registers,

signal transfer lines extending from said registers to said status analyzing unit, and

means in said registers for transferring the signal content thereof to said status analyzing unit in response to a status transfer signal.

6. The data processing system set forth in claim 5 wherein a predetermined number of said stages are connected to said respective OR circuits, said predetemined number being less than all of the states in at least one of said registers.

7. The data processing system set forth in claim 4 wherein said registers are shift registers, means serially connecting all of said shift registers to form a string of such shift registers whereby signal contents of one register are shifted through all of the remaining registers, and

a data connection from said one register to said status analyzing unit for transferring status signals from all of said shift registers in a serial fashion.

8. The data processing system set forth in claim 4 wherein each of said ones of said stages being set by said OR circuits respectively being connected to another of said OR circuits except that one of said registers does not have a one of said stages.

9. The data processing system set forth in claim 4 wherein each of said registers is a shift register,

means interconnecting said shift registers for forming a serial string of said shift registers whereby signal contents of all of said registers can be shifted through a one of said shift registers,

said a one shift register having its corresponding OR circuit connected to said status analyzing unit and its output connected to said status analyzing unit whereby said status analyzing unit receives status signals serially from said a one shift register,

a second one of said shift registers not receiving signals from said OR circuits,

said plurality of shift registers less said second one having an end one of said respective stages receiving signals from said OR circuit of an adjacent one of said shift registers whereby the pattern of status signals in said end one stages indicate unit in error, and

means for serially shifting the status signals through said shift registers to said status analyzing units.