Methods and apparatus for rejection of interference in a digital communications system

• US 4,101,834 A
• Filed: 09/13/1976
• Issued: 07/18/1978
• Est. Priority Date: 09/13/1976
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Stutt, Charles A., Rankin, Richard W.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US05/722,551
• Time in Patent Office: 673 Days
• Field of Search: 331/1 R, 331/18, 331/19, 178/69.1, 178/53, 179/15 BS, 179/15 BL, 325/17, 325/58, 325/63, 325/418, 325/419, 325/421, 325/41, 325/42, 325/39, 325/40, 325/43, 325/44, 325/52, 325/141, 325/143, 325/164, 340/167 R, 340/310 R, 340/310 A, 358/12, 358/13
• US Class Current: 370/482
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 2203/5491 using filtering and bypassing
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 25/45 using electronic distributors
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

A digital communications system of the type transmitting data on a plurality of modulated FDM carriers interspersed between harmonics of a system-wide signal and utilizing a main synchronized detector at a receiving end, is immunized to signal degradation due to reception of "noise" from both the shifting of signal harmonics and the modulation sidebands of adjacent carriers into the passband of the desired communications signal during at least synchronization acquisition by methods of interference minimization including: emplacing each data carrier at a frequency mid-way between adjacent harmonics; locking the frequency of the data carrier to the system-wide signal frequency to maintain the communications frequency exactly mid-way between two adjacent harmonics of the latter signal; transmitting the data in digital form and modulating each data carrier at a baud essentially equal to an exact even submultiple of the system-wide potentially-interfering signal, and detecting the transmitted digitally-modulated carrier at the receiving end by use of long-time-constant bandpass filters. Similar integrating filters, having means for discharging the storage elements thereof after each baud time period as determined by a baud clock synchronized to the system-wide signal, are utilized for the main synchronized data detector.

Claims

1. A method for minimizing interference to a data carrier in a data communications system having a potentially-interfering signal system-wide signal at a known frequency (f_S) and harmonics of said system-wide signal, comprising the steps of:

(a) generating said data carrier at a frequency (f_C)substantially midway between an adjacent pair of the N-th and the N+1-st harmonics of said system-wide single signal; and

(b) locking the frequency (f_C) of said data carrier to an odd multiple (2N+1) of the first subharmonic (f_S/2) of the known frequency (f_S) of said single system-wide signal such that f_C =(2N+1)(f_S /2), where N is an integer greater than zero, to maintain the frequency of said data carrier with essentially equal frequency seapration from each of said adjacent pair of harmonics even if said known frequency varies.

2. A method as set forth in claim 1, wherein said system further includes at least one other data carrier, said method further comprising the steps of:

(c) generating each of said at least one other data carriers at a frequency (f_C '"'"') substantially mid-way between each of at least one other pair of harmonics of said known frequency and differing from the pair of harmonics adjacent to said data carrier; and

(d) locking the frequency (f_C '"'"') of each of said at least one other data carriers to a different odd multiple (2N'"'"'+1) of said first subharmonic of said known frequency such that each frequency f_C =(2N'"'"'+1) (f_S /2), where N'"'"' is another integer greater than zero and different for each of said at least one other data carrier and differing from N for said data carrier, to maintain essentially equal frequency separation between each of said at least one other data carriers and each of the associated pair of harmonics of said known frequency even if said known frequency varies.

3. A method as set forth in claim 2, wherein step (d) comprises the steps of:

dividing said known frequency by a factor of two to obtain a first subharmonic;

dividing the frequency of each data carrier by a factor of (2n+1) to obtain a divided carrier frequency, where n is the number of the lower frequency harmonic adjacent to the data carrier frequency (f_c,n) comparing said first subharmonic and each divided carrier frequency to derive a frequency error for each data carrier; and

adjusting the frequency of each data carrier to reduce the frequency error thereof essentially to zero.

4. A method for minimizing interference in a data communications system having a data carrier, at least one other data carrier, and a potentially-interfering system-wide signal at a known frequency, each of said data carrier and said at least one other data carrier simultaneously carrying an associated data sequence, said method comprising the steps of:

(a) generating said data carrier at a frequency substantially midway between an adjacent pair of harmonics of said system-wide signal;

(b) locking the frequency of said data carrier to the known frequency of said system-wide signal to maintain the frequency of said data carrier with essentially equal frequency separation from each of said adjacent pair of harmonics, even if said known frequency varies;

(c) generating each of said at least one other data carriers at a frequency substantially midway between each of at least one other pair of harmonics of said known frequency and differing from the pair of harmonics adjacent to said data carrier;

(d) locking the frequency of each of said at least one other data carriers to said known frequency to maintain essentially frequency separation between each of said at least one other data carriers and each of the associated pair of harmonics of said known frequency, even if said known frequency varies;

(e) digitizing each data sequence;

(f) modulating each of said data carrier and said at least one other data carrier in accordance with the associated digitized data sequence; and

(g) selecting the modulation characteristics to position a null of the modulation envelope of each modulated data carrier at the carrier frequencies of all of the remaining data carriers.

5. A method as set forth in claim 4, wherein step (g) comprises the step of generating at least one baud, each baud being essentially equal to an exact submultiple of said known frequency;

and step (f) further comprises the step of advancing sequential bits of the digitized data sequence at one of said at least one baud to establish a modulation input for means modulating the associated data carrier.

6. A method as set forth in claim 5, further comprising the step of modulating each data carrier at an identical baud.

7. A method as set forth in claim 5, further comprising the step of modulating at least one of the data carriers at a baud differing from the baud utilized in modulating the remainder of said data carriers.

8. A method as set forth in claim 5, further comprising the step of establishing the baud equal to an even integral submultiple of said known frequency.

9. A method as set forth in claim 5, further comprising the steps of:

(h) receiving a selected one of said modulated data carriers at a receiving end;

(i) providing a baud clock at said receiving end;

(j) synchronizing the frequency of said baud clock to said known frequency; and

(k) demodulating said selected modulated data carrier responsive to each of a plurality of successive baud time periods, each equal to a preselected number of cycles of the frequency of said baud clock, to recover the successive values of said digitized data sequence.

10. A method as set forth in claim 9 wherein step (k) comprises the steps of:

providing main data detector means at said receiving end for demulating the selected modulated data carriers; and

initializing said main detector means to preselected initial conditions after each baud time period responsive to the synchronized baud clock to independently detect each baud of said selected modulated data carrier.

11. A method as set forth in claim 10, wherein said demodulating means comprises at least one integrating means and said initializing step further comprises the step of discharging said integrating means to said preselected initial conditions at the conclusion of a preselected number of said baud time periods.

12. A method as set forth in claim 9, wherein step (f) further comprises the step of preferentially reversing the phase of each data carrier in accordance with the occurrence of a first value of the associated digitized data sequence and at an associated baud equal to said exact submultiple of said known frequency;

and further comprising the steps of providing a pair of said integrating means;

discharging alternating ones of said pair of integrating means at the beginning of alternating ones of said baud time periods;

providing means for coupling said received data carrier to alternating ones of said pairs of integrating means associated alternating ones of said baud periods, each said integrating means maintaining an output thereof at a constant value while said received data carrier is coupled to the remaining integrating means; and

multiplying the outputs of said pair of integrating means together to recover the digitized data sequence.

13. A digital communications system for the transmission of data in media having a potentially-interfering system-wide signal of known frequency, said system comprising:

transmitting means including first means for generating a data carrier at a frequency essentially midway between a pair of adjacent harmonics of said known frequency;

second means responsive to said known frequency for locking the frequency of said first means exactly midway between said pair of adjacent harmonics;

third means for generating a baud essentially equal to an even integer submultiple (m) of said known frequency, where m is greater than 1;

fourth means for storing a data sequence to be transmitted, said fourth means having an output at which sequential single bits of said data sequence are present responsive to sequential cycles of said baud;

fifth means for varying an electrical parameter of said data carrier responsive to said sequential single bits at said output of said fourth means, said fifth means having an output coupled to the transmission media of said system; and

receiving means comprising sixth means for acquiring said baud at the initiation of a data transmission of said data carrier;

seventh means for coupling said sixth means to said media; and

eighth means coupled to said seventh means for synchronously demodulating said data carrier responsive to the baud established by said sixth means.

14. A system as set forth in claim 13, wherein said first means comprises a voltage controlled oscillator having an output frequency substantially proportional to the magnitude of an input voltage;

and said second means comprises first divider means for dividing said known frequency by a factor of two;

second divider means for dividing the frequency of said first means by a factor of (2n+1), where n is an integer greater than one; and

means coupled to said first and second divider means for comparing the pair of divided frequencies to derive a voltage having an amplitude substantially proportional to the frequency error between the pair of divided frequencies, said derived voltage being applied as said input voltage of said first means to reduce said frequency error essentially to zero.

15. A system as set forth in claim 13, wherein said third means comprises a frequency counter having an input and an output, said input receiving said known frequency, said output being alternatively enabled to one of first and second states during counting of each sequential group of m cycles of said known frequency.

16. A system as set forth in claim 13, wherein said sixth means comprises means for integrating a received data carrier;

means for generating a sampling frequency;

means for sampling the integrated receive data carrier at said sampling frequency;

means for detecting a change in the magnitude of said electrical parameter for sequential samples of said received data carrier;

means for generating a multiple of said known frequency; and

means enabled by said detecting means for dividing said multiple of said known frequency by a preselected number to generate a waveform having said baud.

17. A system as set forth in claim 16, wherein said detecting means is adapted to detect a change in polarity of the slope of said integrated received data carrier to enable said dividing means.

18. A system as set forth in claim 16, wherein the electrical parameter varied by said fifth means is the phase of said data carrier;

said eighth means comprising;

first and second integrator means each having an input and an output;

means associated with each of said first and second integrator means for indenpendently establishing initial conditions of each integrator output responsive to different ones of the odd-numbered and even-numbered pulses of the waveform generated by said sixth means;

switch means for alternatively coupling said seventh means to the input of one of said first and second integrator means at said baud;

the output of each integrating means being adapted to be held constant at a value established thereat immediately prior to the remaining one of said integrator means receiving the associated initial-condition-establishing pulse and until recept of next subsequent pulse thereafter; and

means for multiplying together the outputs of said first and second integrator means to derive a signal indicative of the phase of the data carrier received at said receiving means.

19. A system as set forth in claim 18, further comprising means for sampling the output of said multiplying means immediately prior to the receipt of each waveform edge and for storing the value of the sampled output to establish the value of each sequential bit of said data sequence.