Data transmission system using analog to pulse width to digital conversion

• US 4,103,337 A
• Filed: 11/17/1976
• Issued: 07/25/1978
• Est. Priority Date: 11/17/1976
• Status: Expired due to Term

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Whiteside, Arliss Eugene
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/742,972
• Time in Patent Office: 615 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 340/52 F, 340/147 C, 340/151, 340/177 CA, 340/177 VC, 340/177 VA, 340/183, 340/408, 179/15 BL
• US Class Current: 340/870.21
• CPC Class Codes: G08C 19/22 by varying the duration of individual pulses
• CPC Class Codes: H04Q 9/16 by predetermined number of pulses

Abstract

A data transmission system using analog to pulse width to digital conversion for transmitting data generated by an analog sensor to a digital processor is disclosed. A data request signal generated by the digital processor is gated by a processor interface circuit along a single wire data transmission line to a remote sensor activating both the sensor and its associated interface electronics. The data request signal also provides electrical power to the sensor and sensor interface electronics eliminating the need for separate electrical power leads. The sensor interface electronics after a period of time determined by the value of the analog signal generated by the sensor generates a low impedance to ground signal on the data transmission line. The low impedance to ground signal is detected by the processor interface circuit which terminates the transmission of the data request signal. The processor interface circuit further includes a pulse width to digital converter generating digital data indicative of the duration the data request signal is transmitted. More than one sensor may interface the single data transmission line and each sensor interface may be individually activated by interrogation signals generated by the digital processor.

Claims

1. A data transmission system comprising:

digital processor means for processing digital data to produce an output, said digital processor means further including means for periodically generating data request signals having a predetermined pulse duration indicative of a request for new digital data;

sensor means for generating analog data having a value indicative of a sensed condition;

sensor interface means powered by said data request signals for generating a ground signal a determinable time after the beginning of said data request signal in response to said analog data, said ground signal being a low impedance to ground and said determinable time between the beginning of said data request signal and said ground signal being indicative of the value of said analog data;

processor interface means, receiving said data request signals from said digital processor means and said ground signal from said sensor interface means for generating digital data indicative of said determinable time between the beginning of said data request signal and said ground signal;

said processor interface means further including means for gating said data request signals to said sensor interface means and means for transmitting said digital data to said digital processor means;

a single data transmission line interconnecting said sensor interface means and said processor interface means for transmitting said data request signal and said ground signal back and forth between said sensor interface means and said processor interface means.

2. The data transmission system of claim 1 wherein said sensor means comprises a plurality of sensors generating analog data indicative of a like plurality of sensed conditions and said sensor interface means comprises a like plurality of associated sensor interface means wherein one associated interface means interfaces each of said plurality of sensor means, and each of said data request signals comprises a sequentially generated coded interrogation signal followed by a data signal where each coded interrogation signal uniquely identifies one associated sensor interface means, each of said associated sensor interface means comprises:

converter means powered by said data signal for generating said ground signal in response to analog data generated by the sensor means associated therewith after a time determinable from the value of said analog signal; and

decoder means for transmitting said data signal to said converter means in response to the interrogation signal uniquely identifying said associated sensor interface means, said decoder means further transmitting the ground signal generated by the converter means to said single data transmission line.

3. The data transmission system of claim 2 wherein each of said coded interrogation signals comprises a plurality of interrogation pulses, and each associated sensor interface means is identified by a predetermined number of interrogation pulses, said decoder means comprises

first means for generating a switch signal in response to a predetermined number of interrogation pulses and said data signal;

and

bistable means connected to said data transmission line and receiving said interrogation signals and said data signals, said bistable means having a first state blocking said interrogation signals and switchable to a second state in response to said switch signal to transmit said data signal to said converter means and to transmit said ground signal to said data transmission line, said bistable means further operative to return to said first state when said data signal is terminated.

4. The data transmission system of claim 3 wherein said first means comprises

a shift register having a number of sequential storage locations predetermined by the number of interrogation pulses identifying said associated sensor interface means for sequentially shifting a logical ONE data bit from one storage location to an adjacent storage location in response to each of said interrogation pulses and said data signals;

circuit means for inputting a logical ONE bit of data into the first storage location of said shift register; and

gate means responsive to the logical state of the data bit in the last storage location in said shift register and said data signal for generating said switch signal when the state of the bit present in the last storage location of the shift register is a logical ONE and said subsequent data signal is being received;

wherein at the beginning of each coded interrogation signal, the shift register has a logic ONE data bit stored in the first storage location; and

wherein said bistable means is a flip flop circuit having a power input terminal, a SET input terminal and a set output terminal, wherein said power input terminal is connected to said data transmission line, said SET input terminal is connected to the output of said gate means and receives said switch signal, and said SET output terminal is connected to said converter means.

5. The data transmission system of claim 4 wherein said means for inputting a logical ONE data bit into the first storage location of said shift register is a means for generating a logic ONE data bit in response to the beginning of said data signal, said logic ONE data bit transmitted to the first storage location of said shift register.

6. The data transmission system of claim 4 wherein the first interrogation pulse of said plurality of interrogation pulses has a pluse duration different from the pulse duration of subsequent interrogation pulses, said means for inputting a logic ONE data bit into the first storage location is a means for generating a logic ONE data bit in response to said first interrogation pulse, said logic ONE data bit transmitted to the first storage location of said shift register.

7. The data transmission system of claim 3 wherein said converter means comprises:

a capacitance for storing an electrical charge, said capacitance having a grounded electrode and an input electrode;

means for controlling a current flow from said data signal from the output of said bistable means to the input electrode of said capacitance in response to said analog signal, said current flow charging said capacitance at a rate determined by the value of said analog signal;

means for detecting the charge on said capacitance and for generating a low inpedance between the output of said bistable means and a ground potential to generate said ground signal when the charge on said capacitance exceeds a predetermined value; and

a diode connected between the input electrode of said capacitance and the output of said bistable means to discharge said capacitance when the data signal on the output of said bistable means is terminated.

8. The data transmission system of claim 2 wherein said processor interface means comprises:

interrogation signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting only said interrogation signals, said interrogation signal gate means having a first state transmitting said interrogation signals in response to said interrogation signal, and switching to a second state blocking the transmission of said subsequent data signals in response to the termination of said interrogation signal;

data signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting said data signal, said data signal gate means having a first state in response to the first interrogation signal, blocking the transmission of said interrogation signals and switching to a second state transmitting said data signal in response to said data signal;

amplifier means receiving the interrogation signals transmitted by said interrogation signal gate means and the data signal transmitted by said data gate means for amplifying and transmitting said interrogation and data signals to said data transmission line,

line load detector means in circuit relationship with said amplifier means, for generating a switch signal in response to a change in the impedance of said sensor interface means, said switch signal operative to switch said data signal gate means to said first state terminating the transmission of said data signal to said amplifier means; and

pulse width-to-digital converter means for generating digital data in response to the data signal transmitted by said data signal gate means.

9. The data transmission system of claim 8 wherein said interrogation signal is generated within a first predetermined time interval and said data signal is generated in a subsequent time interval, said interrogation signal gate means and said data signal gate means comprises;

gate control circuit means for generating a first gate signal for said first predetermined time interval in response to said interrogation signal and for generating a second gate signal after the termination of said first predetermined time interval;

a first gate circuit receiving said interrogation signal and said data signal for transmitting only said interrogation signal in response to said first gate signal; and

a second gate circuit receiving said interrogation signal and said data signal for transmitting only said data signal in response to said second gate signal;

wherein said first gate circuit and said gate control means comprises said interrogation signal gate means, and said second gate circuit and said control means comprises said data signal gate means.

10. The data transmission system of claim 9 wherein gate control circuit means comprises:

a first one shot multivibrator means for generating said first gate signal in response to said interrogation signal; and

a second one shot multivibrator means for generating said second gate signal in response to the termination of said first gate signal.

11. The data transmission system of claim 10 wherein said interrogation signal comprises a plurality of interrogation pulse signals and each of said sensor interface means is uniquely identified by a predetermined number of interrogation pulse signals;

said first one shot multivibrator means generates said first gate signal in response to the leading edge of the first interrogation pulse signal in said predetermined number of interrogation pulse signals.

12. The data transmission system of claim 9 wherein said interrogation signal comprises a plurality of interrogation pulse signals and each of said sensor interface means is uniquely identified by a predetermined number of interrogation pulse signals and said gate control circuit means comprises:

a one shot multivibrator, triggered by said interrogation pulse signals and said data signals for generating an output pulse signal in response to the leading edge of said interrogation pulse signals and said data signals a predetermined time after being triggered, said predetermined time being slightly longer than the duration of said interrogation pulse signals;

an AND gate receiving inverted interrogation pulse signals and said output pulse signals for transmitting said inverted pulse signals; and

a flip-flop circuit having a first state generating an output in response to said interrogation pulse signals and said data signals and a second state, terminating said output signal in response to said inverted interrogation pulse signals transmitted by said AND gate.

13. The data transmission system of claim 8 wherein:

said data signal gate means further includes a bi-stable electronic switch having a first stable state transmitting said data signal and switchable to a second stable state blocking the transmission of said data signal in response to a reset signal; and

said line load detector comprises;

a capacitance having one electrode in circuit relationship with said amplifier means to transmit a load signal indicative of a change in the load on said data transmission line;

an amplifier circuit in circuit relationship with the other electrode of said capacitance for generating said reset signal in response to said load signal.

14. The data transmission system of claim 8 wherein said pulse width to digital converter means comprises:

a clock generating clock pulses at a high frequency;

a clock gate circuit for transmitting said clock pulses in response to the data signal transmitted by said data signal gate means; and

means for generating digital data indicative of the number clock pulses received from said clock gate circuit while said clock gate is activated by data signal.

15. A data transmission system for providing digital data to a digital processor having means for generating data request signals indicative of a request for new digital data, comprising:

sensor means for generating analog data having a value indicative of a sensed condition;

sensor interface means receiving said analog data and powered by said data request signals for generating a ground signal a determinable time after receiving said data request signal in response to said analog data, said ground signal being indicative of a low impedance to ground, and said determinable time between the beginning of said request signal and said ground signal being indicative of the value of said analog data;

processor interface means receiving said data request signal from the digital processor and said ground signal from said sensor interface means for generating digital data indicative of said determinable time between the beginning of said data request signal and said ground signal;

said processor interface means further including means for gating said data request signals to said sensor interface means and means for transmitting said digital data to the digital processor; and

a single data transmission line interconnecting said sensor interface means and said processor interface means for transmitting said data request signals and said ground signals back and forth between said sensor interface means and said processor interface means.

16. The system of claim 15 wherein said sensor means comprises a plurality of sensors generating analog data indicative of a like plurality of sensed conditions and said sensor interface means comprises a like plurality of associated sensor interface means wherein one associated interface means interfaces each of said plurality of sensor means, and each of said data request signals comprises a sequentially generated coded interrogation signal followed by a data signal where each coded interrogation signal uniquely identifies one associated sensor interface means, said associated sensor interface means comprises:

converter means powered by said data signal for generating said ground signal in response to analog data generated by the sensor means associated therewith after a time determinable from the value of said analog signal; and

decoder means for transmitting said data signal to said converter means in response to the interrogation signal uniquely identifying said associated sensor interface means, said decoder means further transmitting the ground signal generated by the converter means to said single data transmission line.

17. The system of claim 16 wherein each of said coded interrogation signals comprises a plurality of interrogation pulses, and each associated sensor interface means is identified by a predetermined number of interrogation pulses, said decoder means comprises

first means for generating a switch signal in response to a predetermined number of interrogation pulses and said data signal;

and

bistable means connected to said data transmission line and receiving said interrogation signals and said data signals, said bistable means having a first state blocking said interrogation signals and switchable to a second state in response to said switch signal to transmit said data signal to said converter means and to transmit said ground signal to said data transmission line, said bistable means further operative to return to said first state when said data signal is terminated.

18. The system of claim 17 wherein said converter means comprises:

a capacitance for storing an electrical charge, said capacitance having a grounded electrode and an input electrode;

means for controlling a current flow from said data signal from the output of said bistable means to the input electrode of said capacitance in response to said analog signal, said current flow charging said capacitance at a rate determined by the value of said analog signal;

means for detecting the charge on said capacitance and for generating a low impedance between the output of said bistable means and a ground potential to generate said ground signal when the charge on said capacitance exceeds a predetermined value; and

a diode connected between the input electrode of said capacitance and the output of said bistable means to discharge said capacitance when the data signal on the output of said bistable means is terminated.

19. The system of claim 18 wherein said processor interface means comprises:

interrogation signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting only said interrogation signals, said interrogation signal gate means having a first state transmitting said interrogation signals in response to said interrogation signal, and switching to a second state blocking the transmission of said subsequent data signals in response to the termination of said interrogation signal;

data signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting said data signal, said data signal gate means having a first state in response to the first interrogation signal, blocking the transmission of said interrogation signals and switching to a second state transmitting said data signal in response to said data signal;

amplifier means receiving the interrogation signals transmitted by said interrogation signal gate means and the data signal transmitted by said data gate means for amplifying and transmitting said interrogation and data signals to said data transmission line,

line load detector means in circuit relationship with said amplifier means, for generating a switch signal in response to a change in the impedance of said sensor interface means, said switch signal operative to switch said data signal gate means to said first state terminating the transmission of said data signal to said amplifier means; and

pulse width-to-digital converter means for generating digital data in response to the data signal transmitted by said data signal gate means.

20. The system of claim 19 wherein said interrogation signal is generated within a first predetermined time interval and said data signal is generated in a subsequent time interval, said interrogation signal gate means and said data signal gate means comprises;

gate control circuit means for generating a first gate signal for said first predetermined time interval in response to said interrogation signal and for generating a second gate signal after the termination of said first predetermined time interval;

a first gate circuit receiving said interrogation signal and said data signal for transmitting only said interrogation signal in response to said first gate signal; and

a second gate circuit receiving said interrogation signal and said data signal for transmitting only said data signal in response to said second gate signal;

wherein said first gate circuit and said gate control means comprises said interrogation signal gate means, and said second gate circuit and said gate control means comprises said data signal gate means.

21. In combination with a digital processor for processing digital data and sensor means generating analog data, wherein the digital processor includes means for generating data request signals requesting new input data and the sensor means generates analog data having a value indicative of sensed conditions, a data transmission system comprising:

sensor interface means powered by said data request signals for generating a ground signal a determinable time after receiving said data request signal in response to said analog data, said ground signal being indicative of a low impedance to ground, and said determinable time between the beginning of said data request signal and said ground signal being indicative of the value of said received analog data;

processor interface means, receiving said data request signal from the digital processor and said ground signal from said sensor interface means for generating digital data indicative of said determinable time between the beginning of said data request signal and said ground signal;

said processor interface means further including means for gating said data request signals to said sensor interface means and means for transmitting said digital data to the digital processor; and

a single data transmission line interconnecting said sensor interface means and said processor interface means for transmitting said data request signals and said ground signals back and forth between said sensor interface means and said processor interface means.

22. The combination of claim 21 wherein said sensor means comprises a plurality of sensors generating analog data indicative of a like plurality of sensed conditions and said sensor interface means comprises a like plurality of associated sensor interface means wherein one associated interface means interfaces each of said plurality of sensor means, and each of said data request signals comprises a sequentially generated coded interrogation signal followed by a data signal where each coded interrogation signal uniquely identifies one associated sensor interface means, said associated sensor interface means comprises:

converter means powered by said data signal for generating said ground signal in response to analog data generated by the sensor means associated therewith after a time determinable from the value of said analog signal; and

decoder means for transmitting said data signal to said converter means in response to the interrogation signal uniquely identifying said associated sensor interface means, said decoder means further transmitting the ground signal generated by the converter means to said single data transmission line.

23. The combination of claim 22 wherein each of said coded interrogation signals comprises a plurality of interrogation pulses, and each associated sensor interface means is identified by a predetermined number of interrogation pulses, said decoder means comprises

first means for generating a switch signal in response to a predetermined number of interrogation pulses and said data signal;

and

bistable means connected to said data transmission line and receiving said interrogation signals and said data signals, said bistable means having a first state blocking said interrogation signals and switchable to a second state in response to said switch signal to transmit said data signal to said converter means and to transmit said ground signal to said data transmission line, said bistable means further operative to return to said first state when said data signal is terminated.

24. The combination of claim 23 wherein said first means comprises

a shift register having a number of sequential storage locations predetermined by the number of interrogtion pulses identifying said associated sensor interface means for sequentially shifting a logical ONE data bit from one storage location to an adjacent storage location in response to each of said interrogation pulses and said data signals;

circuit means for inputting a logical ONE bit of data into the first storage location of said shift register; and

gate means responsive to the logical state of the data bit in the last storage location in said shift register and said data signal for generating said switch signal when the state of the bit present in the last storage location of the shift register is a logical ONE and said subsequent data signal is being received;

wherein at the beginning of each coded interrogation signal, the shift register has a logic ONE data bit stored in the first storage location; and

wherein said bistable means is a flip flop circuit having a power input terminal, a SET input terminal and a SET output terminal, wherein said power input terminal is connected to said data transmission line, said SET input terminal is connected to the output of said gate means and receives said switch signal, and said SET output terminal is connected to said converter means.

25. The combination of claim 24 wherein said converter means comprises:

a capacitance for storing an electrical charge, said capacitance having a grounded electrode and an input electrode;

means for controlling a current flow of said data signal from the output of said bistable means to the input electrode of said capacitance in response to said analog signal, said current flow charging said capacitance at a rate determined by the value of said analog signal;

means for detecting the charge on said capacitance for generating a low impedance between the output of said bistable means and a ground potential to generate said ground signal when the charge on said capacitance exceeds a predetermined value; and

a diode connected between the input electrode of said capacitance and the output of said bistable means to discharge said capacitance when the data signal on the output of said bistable means is terminated.

26. The combination of claim 25 wherein said processor interface means comprises:

interrogation signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting only said interrogation signals, said interrogation signal gate means having a first state transmitting said interrogation signals in response to said interrogation signal, and switching to a second state blocking the transmission of said subsequent data signals in response to the termination of said interrogation signal;

data signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting said data signal, said data signal gate means having a first state in response to the first interrogation signal, blocking the transmission of said interrogation signals and switching to a second state transmitting said data signal in response to said data signal;

amplifier means receiving the interrogation signals transmitted by said interrogation signal gate means and the data signal transmitted by said data gate means for amplifying and transmitting said interrogation and data signals to said data transmission line;

line load detector means in circuit relationship with said amplifier means, for generating a switch signal in response to a change in the impedance of said sensor interface means, said switch signal operative to switch said data signal gate means to said first state terminating the transmission of said data signal to said amplifier means; and

pulse width-to-digital converter means for generating digital data in response to the data signal transmitted by said data signal gate means.

27. The combination of claim 26 wherein said interrogation signal is generated within a first predetermined time interval and said data signal is generated in a subsequent time interval, said interrogation signal gate means and said data signal gate means comprises;

gate control circuit means for generating a first gate signal for said first predetermined time interval in response to said interrogation signal and for generating a second gate signal after the termination of said first predetermined time interval;

a first gate circuit receiving said interrogation signal and said data signal for transmitting only said interrogation signal in response to said first gate signal; and

a second gate circuit receiving said interrogation signal and said data signal for transmitting only said data signal in response to said second gate signal;

wherein said first gate circuit and said gate control means comprises said interrogation signal gate means, and said second gate circuit and said gate control means comprises said data signal gate means.

28. In combination with a digital processor for processing digital data to produce an output and a plurality of sensors generating output data indicative of sensed conditions, wherein said digital processor includes means for generating data request signals indicative of requests for new data from the sensor, each of such data request signals comprising an interrogation signal uniquely identifying the particular sensor from which new data is requested, followed by a data signal an improved data transmission system comprising:

interrogation signal gate means sequentially receiving said interrogation and data signals from said digital processor for selectively transmitting only said interrogation signals, said interrogation signal gate means having a first state transmitting only said interrogation signals and switching to a second state in response to said data signal blocking the transmission of said subsequent data signals;

data signal gate means sequentially receiving said interrogation signal and said data signals from the digital processor for selectively transmitting only said data signals, said data signal gate means having a first state in response to said interrogation signal blocking the transmission of said interrogation signals and switching to a second state in response to said data signal transmitting said data signals;

amplifier means having an input and an output, said amplifier means receiving at said input the interrogation signals transmitted by the interrogation signal gate means and the data signal transmitted by the data gate means for amplifying and transmitting said interrogation and data signals via said output;

line load detector means in circuit relationship with said amplifier means for generating a switch signal in response to a change in the impedance at the output of the amplifier means, said switch signal operative to switch said data signal gate means to said first state terminating the transmission of said data signal to said amplifier means;

pulse width to digital converter means for generating digital data in response to the data signal transmitted by said data signal gate means;

a single data transmission line connected to the output of said amplifier means for transmitting said interrogation and data signals;

converter means powered by said data signal for generating a ground signal indicative of a low impedance to ground in response to the output data of said sensors at a time determinable from the value of said output data and wherein one converter means is associated with each of said plurality of sensors and is associated therewith; and

decoder means connected to said single data transmission line for transmitting said data signal to said converter means in response to the interrogation signal uniquely identifying the sensor associated with said converter means, said decoder means further transmitting said ground signals generated by the converter means to the output of said amplifier means via said single data transmission line.

29. The combination of claim 28 wherein each interrogation signal comprises a predetermined number of short pulse signals wherein the predetermined number of pulses in each interrogation signal uniquely identifies the sensor from which new data is requested, said decoder means comprises

shift register means, having a number of sequential storage locations predetermined by the number of pulses in the interrogation signal identifying the particular sensor associated with said decoder means, said shift register means sequentially shifting a logical ONE data bit from one storage location to an adjacent storage location in response to each of said interrogation pulses, said shift register means further storing the logical ONE data bit in the last storage location when the interrogation signal identifying the particular sensor associated with the decoder means is received;

bistable means connected to said data transmission line and receiving said interrogation signals and said data signals for generating a logical ONE data bit in response to receiving said data signal;

an AND gate for generating a signal in response to a logical ONE data bit generated by said bistable means and the presence of a logical ONE data bit in last storage location of the shift register;

a flip-flop circuit having a first state upon the application of electrical power and switchable to a second state in response to the signal generated by said AND gate, said flip flop circuit transmitting said data signal to said converter means; and

means for inputing a logical ONE data bit into the first storage location of said shift register in response to a logical ONE data bit being generated by said bistable means.

30. A method for transmitting data between a digital processor and a plurality of sensors for generating sensor data indicative of sensed conditions, wherein said digital processor includes means for sequentially generating data request signals indicative of requests for new data from the sensors, wherein each of said data request signals comprises an interrogation signal uniquely identifying the particular sensor from which the new data is requested followed by a data signal, comprising the steps of:

gating the data request signal generated by the digital processor with gate means to separately transmit the interrogation signal from the data signal;

sequentially amplifying said interrogation and data signals to generate amplifier interrogation and data signals;

detecting a change in the amplified data signal by means of a line load detector to generate a switch signal;

deactivating said gate means with said switch signal to terminate the transmission of said data signal;

gating clock pulses to a counter with said data signal to convert said data signals to digital data;

transmitting said digital data to said digital processor in response to the termination of the transmission of said data signal;

transmitting said amplified interrogation and data signals to remote decoder means via a single data transmission line;

decoding said interrogation signal with said decoder means, to activate a switch transmitting said data signal to an associated converter means when the interrogation signal identifies the sensor associated with the decoder means;

generating a ground signal by means of said converter means when the integrated value of the sensor data generated by the sensor associated therewith reaches a predetermined value, said ground signal indicative of a low impedance to ground,

transmitting said ground signal back to said line load detector via said single data transmission line

whereby said ground signal is detected by said line load detector which generates a switch signal terminating the transmission of said clock signal to said counter.