Extended target-log CFAR processor

• US 4,104,633 A
• Filed: 04/18/1977
• Issued: 08/01/1978
• Est. Priority Date: 04/18/1977
• Status: Expired due to Term

• Current Assignee: ITT Corporation (ITT, Inc.)
• Original Assignee: International Telephone & Telegraph Corp. (ITT, Inc.)
• Inventors: Donahue, Thomas H., Chaney, John F.
• Primary Examiner(s): Tubbesing, T.H.
• Application Number:
  US05/788,134
• Time in Patent Office: 470 Days
• Field of Search: 343/7 A
• US Class Current: 342/93
• CPC Class Codes: G01S 7/2922 by using a controlled threshold

Abstract

A constant false alarm rate video processor which uses a tapped delay line operating as a "sliding range window" to provide tap outputs corresponding to the center of the delay line and a predetermined number of discrete range cells on either side thereof. A "least of" circuit is responsive to all taps except the center tap of the delay line and the mininum signal extant on these taps is outputted and substracted (in scale factored form) from the signal of the delay line. The circuit thereby adaptively excludes target and ground clutter bias in providing the CFAR (normalized) signal output of the combination. An additional circuit arrangement is shown for digitally mapping the "least of" signal values over a predetermined threshold. The digital map output converted to analog then provides the scaled "least of" signal to be subtracted from the central range cell and for controlling the threshold of response of the mapper.

Claims

1. A CFAR radar video signal processor comprising:

first means including at least one delay line responsive to said radar video signal and having a predetermined plurality of outputs spaced in time by one range cell of the radar system in which said CFAR processor is being used;

second means including a least of circuit connected to provide an output corresponding to the least of the signals extant on any of said first means outputs except a predetermined centrally located output, in time;

and a differencing circuit responsive to said least of circuit output and to the signal provided by said first means corresponding to a centrally located signal to subtract said least of circuit output from said signal on said centrally located tap to produce a CFAR video output signal.

2. Apparatus according to claim 1 in which said centrally located first means output is defined as being that at which the effective delay is Kτ

and in which the overall delay from input to the most delayed output of said first means is 2Kτ

, and τ

is the duration of a range resolution cell of said radar system.

3. Apparatus according to claim 2 in which the receiver generating said radar video signal contains log video detection means, said video signal thereby being generated as a log video signal.

4. Apparatus according to claim 3 further including a scale factor device in the signal path between the output of said second means and said differencing circuit, the scale factor of said device being selected to provide a predetermined false alarm rate.

5. Apparatus according to claim 3 including selection means responsive to said log video signal for continuously selected as an output the greatest of the signals in two adjacent range cells and for providing said output as the input to said first means.

6. Apparatus according to claim 5 in which said first mean comprises a delay line having a delay of Kτ

connected to said log video ahead of said selection means for providing said centrally located first means output, and in which said first means also includes a tapped delay line of total length 2Kτ

, said taps being spaced by a time τ

.

7. Apparatus according to claim 2 in which said first means comprises a tapped delay line having taps providing inputs to said second means and said differencing circuit.

8. Apparatus according to claim 1 in which the receiver generating said radar video signal contains log video detection means, said video signal thereby being generated as a log video signal.

9. Apparatus according to claim 8 in which a clutter mapping device is inserted in the signal path between said second means and said differencing circuit, said mapping device comprising a memory device and an input threshold circuit therefor to store the outputs of said second means on a two-coordinate basis and by range-azimuth cells, said memory device also synchronously providing integrated clutter signals originating from the output signals of said least of circuit, to said differencing circuit.

10. Apparatus according to claim 9 in which said input threshold device is a digital device providing a binary signal in a first condition corresponding to each signal from said second means in excess of a predetermined amplitude, and providing said binary signal in a second condition at all other times, and in which said memory device comprises means responsive to said threshold device for increasing the stored digital value in said memory in each of said range-azimuth cells by a first predetermined amount in response to each corresponding first condition output from said threshold device, and for decreasing said stored digital value in said memory in each of said range-azimuth cells by a second predetermined amount less than said first predetermined amount in response to each corresponding second condition output from said threshold device, said apparatus further including a digital-to-analog conversion unit synchronously reading said stored digital values and converting them to analog signals for application to said differencing circuit.

11. Apparatus according to claim 1 including selection means responsive to said log video signal for continuously selected as an output the greatest of the signals in two adjacent range cells and for providing said output as the input to said first means.

12. Apparatus according to claim 1 in which a clutter mapping device is inserted in the signal path between said second means and said differencing circuit, said mapping device comprising a memory device and an input threshold circuit therefor to store the outputs of said second means on a two-coordinate basis and by range-azimuth cells, said memory device also synchronously providing integrated clutter signals originating from the output signals of said least of circuit, to said differencing circuit.