Extended target-log CFAR processor
First Claim
1. A CFAR radar video signal processor comprising:
- first means including at least one delay line responsive to said radar video signal and having a predetermined plurality of outputs spaced in time by one range cell of the radar system in which said CFAR processor is being used;
second means including a least of circuit connected to provide an output corresponding to the least of the signals extant on any of said first means outputs except a predetermined centrally located output, in time;
and a differencing circuit responsive to said least of circuit output and to the signal provided by said first means corresponding to a centrally located signal to subtract said least of circuit output from said signal on said centrally located tap to produce a CFAR video output signal.
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Accused Products
Abstract
A constant false alarm rate video processor which uses a tapped delay line operating as a "sliding range window" to provide tap outputs corresponding to the center of the delay line and a predetermined number of discrete range cells on either side thereof. A "least of" circuit is responsive to all taps except the center tap of the delay line and the mininum signal extant on these taps is outputted and substracted (in scale factored form) from the signal of the delay line. The circuit thereby adaptively excludes target and ground clutter bias in providing the CFAR (normalized) signal output of the combination. An additional circuit arrangement is shown for digitally mapping the "least of" signal values over a predetermined threshold. The digital map output converted to analog then provides the scaled "least of" signal to be subtracted from the central range cell and for controlling the threshold of response of the mapper.
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Citations
12 Claims
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1. A CFAR radar video signal processor comprising:
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first means including at least one delay line responsive to said radar video signal and having a predetermined plurality of outputs spaced in time by one range cell of the radar system in which said CFAR processor is being used; second means including a least of circuit connected to provide an output corresponding to the least of the signals extant on any of said first means outputs except a predetermined centrally located output, in time; and a differencing circuit responsive to said least of circuit output and to the signal provided by said first means corresponding to a centrally located signal to subtract said least of circuit output from said signal on said centrally located tap to produce a CFAR video output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification