Electronic telephone system featuring a customer memory within a central control unit connected by bus lines
First Claim
1. In an electronic telephone switching system having peripheral units for carrying signals between subscribers, said peripheral units including a plurality of trunk and tie line circuits, at least one attendant line circuit, a plurality of signaling tone receivers and a plurality of link control circuits, having a plurality of tone generators for applying signal tones to said peripheral units, having speech path and tone switching matrices connected to and operable to interconnect said peripheral units and to interconnect said tone generators with through connections between said peripheral units, having control means constituted by a plurality of components including a central processing unit, a program memory connected to said central processing unit, a program memory connected to said central processing unit, a customer memory connected to said central processing unit, and a scratch pad memory connected to said central processing unit, having system timing means connected to said central processing unit and to said program, customer and scratch pad memories, and having bus lines interconnecting the components of said central control means and other bus lines for connecting said peripheral units to said central control means, the improvement comprising:
- means connecting said customer memory to receive data, command and address signals via said bus lines, said means carrying faster rise time pulses than said othe bus lines, for enabling control by said central control means,circuit means for coupling the data, command and address signals in the form of changing potentials to said customer memory including capacitor means coupling said circuit means to said customer memory, andalternately activated plural transistor switches responsive to differing potentials from said data, command and address signals for supplying potentials to said capacitor means
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Accused Products
Abstract
An electronic telephone switching system is described having peripheral units including a plurality of subscriber and line circuits, a plurality of trunk and tie line circuits, at least one attendant line circuit, a plurality of signaling tone receivers, and a plurality of link control circuits. Switching is carried out by a one wire speech path switching matrix and a one wire tone switching matrix. The system is centrally controlled and includes a central processing unit, a program memory, a scratch pad memory and a customer memory. Information, commands and addresses are communicated between the peripheral units and the central control and within the central control via bus lines. The bus lines between the peripheral units and the central control transmit data with lower rise time pulses than the bus lines interconnecting the components of the central control. Each electronic crosspoint switch has a two terminal conducting path and a control terminal for controlling the state of conduction of the conducting path. Different conducting path terminals of the speech path matrix and tone path matrix crosspoint switches are operated by the same peripheral link unit. The matrix coordinates to be operated are defined by polling the different peripheral units connected to the coordinates in question.
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Citations
1 Claim
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1. In an electronic telephone switching system having peripheral units for carrying signals between subscribers, said peripheral units including a plurality of trunk and tie line circuits, at least one attendant line circuit, a plurality of signaling tone receivers and a plurality of link control circuits, having a plurality of tone generators for applying signal tones to said peripheral units, having speech path and tone switching matrices connected to and operable to interconnect said peripheral units and to interconnect said tone generators with through connections between said peripheral units, having control means constituted by a plurality of components including a central processing unit, a program memory connected to said central processing unit, a program memory connected to said central processing unit, a customer memory connected to said central processing unit, and a scratch pad memory connected to said central processing unit, having system timing means connected to said central processing unit and to said program, customer and scratch pad memories, and having bus lines interconnecting the components of said central control means and other bus lines for connecting said peripheral units to said central control means, the improvement comprising:
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means connecting said customer memory to receive data, command and address signals via said bus lines, said means carrying faster rise time pulses than said othe bus lines, for enabling control by said central control means, circuit means for coupling the data, command and address signals in the form of changing potentials to said customer memory including capacitor means coupling said circuit means to said customer memory, and alternately activated plural transistor switches responsive to differing potentials from said data, command and address signals for supplying potentials to said capacitor means
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Specification