Interface system providing interfaces to central processing unit and modular processor-controllers for an input-output subsystem

• US 4,106,092 A
• Filed: 09/29/1977
• Issued: 08/08/1978
• Est. Priority Date: 09/30/1976
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Corp (Unisys Corporation)
• Inventors: Millers, Donald A. II
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/837,918
• Time in Patent Office: 313 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/64
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A sub-interface system within an Input-Output Subsystem of a digital data processing system. The interface subsystem comprises a Main System Interface of a central processing unit working with the distribution-control means of a Base Module housing a group of Line Control Processors (individual Intelligent I/O Interface units) dedicated to a specific peripheral device. The Main System Interface is designated as an IOT, or Input-Output Translator, and translates input-output instructions into proper form for delivery to a particular intelligent interface unit which can execute the instructions. The IOT provides a data link identifier to identify each particular data-transfer transaction and receives result information from the Line Control Processor and Base Module to keep the Main System informed of the status or completion of each individual data-transfer operation. The Input-Output Translator provides a selection of priority to be given to competing Line Control Processor requests for access to Main Memory and communicates with individual Line Control Processors in their control of data-transfer operations between various peripheral devices and the Main Memory of the System.

Claims

1. In a digital processing system for controlling the transfer of data between a plurality of peripheral units and a main host system which includes a main memory and main processor, wherein each peripheral unit is controlled by a Line Control Processor, and a plurality of Line Control Processors are organized into a Base Module, and a plurality of such Base Modules are connected to said main host system through individual message level interfaces, an input-output translator interface unit in said main system for interfacing said plurality of Base Modules and Line Control Processors, said input-output translator interface comprising:

(a) means to receive a plurality of input-output instructions from said processor and main memory and to receive address signals for selecting a particular Base Module and particular Line Control Processor for establishing communcations with a particular peripheral unit;

(b) connection means to establish a data path from said main system to an addressed Line Control Processor;

(c) data transfer means to transfer control data and information data between main memory and an addressed Line Control Processor;

(d) means to assemble a descriptor link signal to serve as an identifier for each specific input-output data transfer cycle instruction from said main procesor;

(e) scratchpad memory means having a particular portion of its memory reserved for each Line Control Processor, said scratchpad memory storing the beginning and ending addresses of any given data field in main memory plus reserved scratchpad memory sections in each portion for signal information as to the status of each input-output transfer cycle command initiated by said main processor.

2. The input-output translator interface of claim 1 including:

means to translate instructions from said processor and main memory into a common format usable by each of said Line Control Processors.

3. the input-output translator interface of claim 1 including:

an operations code buffer having two portions for storage of instructional OP-codes, whereby two separate instructions can be simultaneously executed to facilitate data transfer operations between the main system and two different Line Control Processors.

4. The input-output translator interface of claim 1 wherein said scratchpad memory means provides a reserved channel area of storage for each individual Line Control Processor in the overall system and wherein each reserved channel area includes storage areas for:

(e1) the beginning and the ending addresses of the memory data field involved;

(e2) flag signals indicative of errors detected;

(e3) result signals indicating the status of completion or incompletion of any given input-output data transfer instruction.

5. The input-output translator interface of claim 1 including:

Op-code buffer means to accept and store at least two input-output data transfer instructions, and wherein said scratchpad memory includes storage means;

(i) dedicated for each Line Control Processor for storing main memory addresses of sections of main memory to be used;

(ii) for result signal words for indicating the completion status of a given input-output command;

(iii) for storing error flag signals; and

(iv) for storing descriptor link signals for identifying each specific input-output data transfer command.

6. The input-output translator interface of claim 1 wherein:

each of said Line Control Proocessors in each Base Module generates a pre-assigned priority signal; and

said input-output translator interface includes priority determination means to compare the priority signals of competing Line Control Processors requesting memory access in order to select which Line Control Processor will be granted access to main memory.

7. In a digital processing system for controlling the transfer of data between a plurality of peripheral units and a main host system, which includes a main memory and main processor, wherein each peripheral unit is controlled by a Line Control Processor, and a plurality of Line Control Processors are organized into a Base Module, and a plurality of such Base Modules are connected to said main host system through individual message level interfaces, an input-output translator interface unit in said main system for interfacing said plurality of Base Modules and Line Control Processors, and input-output translator interface comprising:

(a) means to receive an input-output instruction from said main processor and translate it into a standard format usable by any of said lIne Control Processors in said system;

(b) a scratchpad memory having a plurality of reserved channel portions, each channel portion reserved for a particular Line Control Processor in the system, each of said reserved portions dedicated for storage of data and information relating to a specific Line Control Processor;

(c) descriptor link register connected to said scratchpad memory and serving to store an identifier signal for each input-output command initiated by said processor;

(d) means for establishing a data path between main memory and a Line Control Processor addressed from said main system;

(e) means to establish a data path from an access-requesting Line Control Processor to said main memory;

(f) transfer means for transferring said descriptor link identifier in said descriptor link register to an addressed Line Control Processor;

(g) data transfer means for controlling the transfer of data between main memory and a selected Line Control Processor;

said data transfer means including means responsive to signals from said Line Control Processor to disconnect said Line Control Processor from main memory;

(h) reconnection means for re-establishing a data path between an access-requesting Line Control Processor and said main memory, said reconnection means including;

priority resolving means for resolving priority of access of access-requesting Line Control Processors for connection to, or reconnection to, main memory when simultaneous requests for memory access are received.

8. The input-output translator interface of claim 7 wherein said scratchpad memory includes:

(b1) means for storing a beginning (A) address and an ending (B) address to define the section of main memory being utilized in a specific input-output data transfer instruction, and, wherein said input-output translator interface further includes;

(i) means, during a forward data transfer operation, to increment said beginning (A) address by four digits for each word transferred or to increment said beginning (A) address by two digits for each character transferred;

(j) means, during a backward data transfer operation, to decrement said ending (B) address by four digits for each word transferred or by two digits for each character transferred.

9. The input-output translator of claim 7 wherein said descriptor link register includes means to receive a descriptor link identifier signal from an access-requesting Line Control Processor which has been granted access to main memory.

10. In a digital processing system for controlling the transfer of data between a plurality of peripheral units and a main host system, which main system includes a main memory and processor, and where each peripheral unit is controlled by a Line Control Processor, and a plurality of such Line Control Processors are organized into a Base Module, and wherein a plurality of such Base modules are connected to said main host system through individual message level interfaces, an input-output translator interface unit in said main system for interfacing said plurality of Base Modules and Line Control Processors, said input-output translator interface comprising:

(a) a plurality of base drivers connecting to a plurality of Base Module units via individual message level interfaces;

(b) a first (DA) and a second (DB) data bus connecting said base drivers to an output buffer switching unit;

(c) an output buffer switching unit connecting said first (DA) and said second (DB) data buses to;

(c1) a connection module;

(c2) a reconnection module;

(c3) a first and second data transfer module means;

(d) an initiation module having means for receiving;

(i) instruction signals;

(ii) Base Module address; and

(iii) Line Control Processor address signals;

from the main host processor;

said initiation module including means for;

(i) conveying instruction OP-codes to said connection module via an operations-buffer, and

(ii) conveying memory location address signals to said scratchpad memory;

(e) an operations-buffer including a first and a second operations-buffer section for storing first and second instruction OP-codes received from said initiation module and including means to convey said OP-codes to said connection module;

(f) a scratchpad memory for storing memory addresses received from said initiation module, said scratchpad memory including a plurality of sections whereby each section is dedicated to a particular Line Control Processor, and each section stores memory addresses related to each input-output data-transfer instruction related to its particular Line Control Processor;

(g) said connection module having means for receiving Base Module and Line Control Processor addresses and for initiating signals to said output buffer switching unit to establish connection to an addressed Line Control Processor, and including means to transmit, to an addressed Line Control Processor, an instruction code signal and a descriptor-link identifier signal to identify the particular input-output instruction;

(h) said reconnection module having means to receive access-request signals from a Line Control Processor seeking main memory access, and including;

means for signaling said data transfer module means to establish connection to an available non-busy data transfer module;

means to select priority of access among Line Control Processors simultaneously requesting access to memory;

logic means to connect a requesting Line Control Processor to a selected data transfer module for data transfer operations;

(i) data transfer module means including;

(i1) a plurality of data transfer modules;

(i2) a descriptor link register to receive descriptor link identifier signals to identify the particular input-output data-transfer instruction involved and to identify the portion of scratchpad memory where specific address memory information for a particular instruction to a particular Line Control Processor is stored;

(i3) means to transfer data between main memory and a connected Line Control Processor;

(j) a memory Read bus and a memory Write bus connecting said main memory to said plurality of data transfer modules.

11. The input-output translator interface of claim 10 wherein said output buffer switching unit includes:

a first and a second descriptor information register, each of said registers storing;

an instruction OP-code, variant signals, data signals to provide translation ir inhibit translation, a backwards-forwards flag signal, address signals of a particular Line Control Processor in a particular Base Module, and the file address of the input-output instruction.

12. The input-output translator unit of claim 10 wherein each Line Control Processor in said system generates status count signal information which is conveyed to said input-output translator interface unit to regulate the transmission, or cessation, of data transfer cycles.

13. The input-output translator interface unit of claim 10 wherein said Line Control Processor, after each data transfer cycle, transmits a result descriptor word signal to said input-output translator interface, which signal defines the status of the particular input-output instruction cycle as being complete, incomplete or in error, and wherein said input-output translator includes:

means to transmit said result descriptor word signal to be dedicated portion of main memory.

14. In a digital processing system for controlling the transfer of data between a plurality of peripheral units and a main host system, which main system includes a main memory and processor, and where each peripheral unit is controlled by a Line Control Processor and a plurality of such Line Control Processors are organized into a Base Module, and wherein a plurality of such Base Modules are connected to said main host system through individual message level interfaces, an input-output translator interface unit in said main system for interfacing said plurality of Base Modules and Line Control Processors, said input-output translator interface comprising:

A. a scratchpad memory for storing main memory addresses related to each particular Line Control Processor;

B. an operations-buffer (OP buffer) for storing OP-codes representing each input-output command initiated by said processor;

C. base driver means connecting to each of a plurality of Base Modules via a message level interface;

D. a first (DA) and second (DB) data bus connecting said base driver means to an output buffer switching means;

E. output buffer switching means connecting said first (DA) and second (DB) data buses to;

a Connection Module, a Reconnection Module, and a Data Transfer Module;

F. a memory read bus and a memory write bus connecting said Data Transfer Module to main memory;

G. an Initiation Module including;

(Ia) means to receive from said main processor an OP-code, I/O command signal, Base Module address and Line Control Processor address;

(Ib) means to receive variant code signals for optional variations in the I/O command OP-code signal;

(Ic) means to receive a beginning (A) address of main memory location to be utilized and to store address (A) in scratchpad memory;

(Id) means to receive an ending (B) address of main memory location to be utilized and to store said (B) address in scratchpad memory;

(Ie) signal generation means, for transfer of signals to said connection module, to initiate a connection to an addressed Line Control Processor.

H. a Connection Module including;

(Ca) means to receive a Base Module address and Line Control Processor address and to initiate a connection signal to an addressed Line Control Processor;

(Cb) signal means to enable said base driver means to connect an addressed Line Control Processor to a Data Transfer Module;

(Cc) means to assemble and to send, to a connected Line Control Processor, the OP-code and a descriptor link identifier which identifies the particular I/O command involved;

(Cd) means to enable said Data Transfer Module for data transmission between main memory and a connected Line Control Processor;

(Ce) means to disconnect from a connected Line Control Processor.

I. a Data Transfer Module including;

(Da) means to receive a descriptor link indentifier from said Reconnection Module;

(Db) means to fetch the said beginning (A) and ending (B) addresses from said scratchpad memory;

(Dc) means to request access to main memory and to receive data from a connected Line Control Processor into said output buffer switching means;

(Dd) means to send address (A) to main memory, and including means to compare said beginning (A) and ending (B) addresses;

(De) means to inrement said (A) address for each word transferred and to restore an incremented address (A) to a memory address register in said processor;

(Df) means to transfer data in said output buffer switching means to main memory;

(Dg) means to restore said (A) address to scratchpad memory;

(Dh) means to disconnect a connected Line Control Processor;

J. a Reconnection Module including;

(Ra) means to receive an interrupt request from one or more access-requesting Line Control Processors;

(Rb) means to grant priority to one of said access-requesting Line Control Processors;

(Rc) a descriptor link register to receive and hold a descriptor link identifier from an access-requesting Line Control Processor;

(Rd) means to select an available Data Transfer Module and to connect said access-requesting Line Control Processor to said Data Transfer Module for data transmission between said Line Control Processor and main memory.

15. The input-output translator interface of claim 14 wherein said Data Transfer Module includes:

(Ta) means to receive a descriptor link identifier from said Reconnection Module;

(Tb) means to fetch the said beginning (A) and ending (B) addresses from said scratchpad memory;

(Tc) signal generating means to request access to main memory;

(Td) means to compare said beginning (A) and ending (B) addresses;

(Te) transfer means to transfer address (A) to memory;

(Tf) means to receive an access granted signal from main memory;

(Tg) means to increment said beginning (A) address for each word transferred from memory;

(Th) memory bus means to transfer data from main memory to an information register;

(Ti) an information register to receive data transferred from memory;

(Tj) output buffer switching means to receive data from said information register;

(Tk) transfer means to transmit data from said output buffer switching means to an addressed Line Control Processor.

16. The input-output translator interface of claim 15 wherein said Data Transfer Module includes:

character register means and shift control means for transferring a full word of two characters between said information register means and said output buffer switching means when said address (A) is MOD 4, and for transferring a half word of one character between said information register means and said output buffer means when said address (A) is MOD 2.

17. The input-output translator interface of claims 14 wherein said Data Transfer Module includes:

means to provide system memory access in response to a status count signal from any connected Line Control Processor;

means to receive a result signal from said Line Control Processor indicative of the state of completion or incompletion of an I/O command and to store it in said output buffer switching means;

logic means to transfer said result signal from said output buffer switching means to main memory.