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Interface system providing interfaces to central processing unit and modular processor-controllers for an input-output subsystem

  • US 4,106,092 A
  • Filed: 09/29/1977
  • Issued: 08/08/1978
  • Est. Priority Date: 09/30/1976
  • Status: Expired due to Term
First Claim
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1. In a digital processing system for controlling the transfer of data between a plurality of peripheral units and a main host system which includes a main memory and main processor, wherein each peripheral unit is controlled by a Line Control Processor, and a plurality of Line Control Processors are organized into a Base Module, and a plurality of such Base Modules are connected to said main host system through individual message level interfaces, an input-output translator interface unit in said main system for interfacing said plurality of Base Modules and Line Control Processors, said input-output translator interface comprising:

  • (a) means to receive a plurality of input-output instructions from said processor and main memory and to receive address signals for selecting a particular Base Module and particular Line Control Processor for establishing communcations with a particular peripheral unit;

    (b) connection means to establish a data path from said main system to an addressed Line Control Processor;

    (c) data transfer means to transfer control data and information data between main memory and an addressed Line Control Processor;

    (d) means to assemble a descriptor link signal to serve as an identifier for each specific input-output data transfer cycle instruction from said main procesor;

    (e) scratchpad memory means having a particular portion of its memory reserved for each Line Control Processor, said scratchpad memory storing the beginning and ending addresses of any given data field in main memory plus reserved scratchpad memory sections in each portion for signal information as to the status of each input-output transfer cycle command initiated by said main processor.

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