Failure detection circuit for a vehicle anti-skid braking system

• US 4,106,821 A
• Filed: 10/07/1976
• Issued: 08/15/1978
• Est. Priority Date: 10/01/1975
• Status: Expired due to Term

• Current Assignee: Girling Limited (ZF International UK Ltd.)
• Original Assignee: Girling Limited (ZF International UK Ltd.)
• Inventors: Brearley, Malcolm
• Primary Examiner(s): Blix, Trygve M.
• Assistant Examiner(s): Eisenzopf, Reinhard J.
• Application Number:
  US05/730,423
• Time in Patent Office: 677 Days
• Field of Search: 303/92, 303/96
• US Class Current: 303/122.06
• CPC Class Codes: B60T 8/885 using electrical circuitry

Abstract

An anti-skid braking system including a plurality of independent solenoid energizing circuits which are controlled in accordance with the outputs of sensors on separate wheels of a vehicle, has a failure detection circuit comprising a timer triggered into operation each time any one of the solenoids is energized, and reset when a back e.m.f. generated by the deactivation of any solenoid is detected. If the timer is not reset within a fixed period the system is disabled and a warning lamp is energized. The system also includes a circuit utilizing the back e.m.f. signals for testing the system each time it is switched on.

Claims

1. An anti-skid braking system including a plurality of wheel speed sensors, a plurality of wheel slip detection circuits associated with the respective wheel speed sensors, a plurality of brake release solenoids connected to the respective slip detection circuits so as to energise a solenoid if the corresponding slip detection circuit detects slippage of the associated wheel, and a failure detection circuit comprising solenoid energisation detection means connected to said solenoids and producing an output signal when any one of the solenoids is energised, a timing circuit connected to the solenoid energisation detection means so as to be triggered into operation thereby, warning means operable by said timing circuit if the latter remains in operation for more than a predetermined time, means for detecting the back e.m.f. produced when each solenoid is switched off, and timer circuit reset means controlled by said back e.m.f. detecting means for resetting the timer circuit when any solenoid is switched off.

2. A system as claimed in claim 1 wherein said detection circuit includes power transistors of the emitter follower type, with the solenoids connected as emitter loads of the respective power transistors, said solenoid energisation detector means comprising an OR gate having its inputs connected to the solenoid-emitter junctions.

3. A system as claimed in claim 2 in which said solenoid-emitter junctions are connected by respective biasing resistors to a signal source so that the junctions are normally held at a low voltage by current leakage through the resistor/solenoid circuits, but the potential at a junction will change to provide an input signal to the OR gate if any solenoid becomes open circuit.

4. A system as claimed in claim 2 in which the back e.m.f. detection means includes a further transistor of opposite conductivity type to the emitter follower power transistor with its emitter connected to the collector of the power transistor, its base connected by a Zener diode to the base of the power transistor and its collector connected by a load resistor to ground, the Zener diode breaking down when there is a back e.m.f. induced in the solenoid at switch off thereof so that base current to the power transistor flows through the emitter-base of the further transistor and the Zener diode, thereby turning on the further transistor and creating a potential difference across the load resistor.

5. A system as claimed in claim 1 further comprising a power trip operated by said timer circuit and arranged to disable the system in the event of the timer circuit producing a fault indicating output.

6. A system as claimed in claim 1, including test means for engaging the solenoids briefly each time the system is switched on and for simultaneously de-energising the solenoids, and means for illuminating a warning lamp for a period, said lamps remaining illuminated if the back e.m.f. detecting means do not simultaneously produce an output signal.

7. A system as claimed in claim 6, in which said test means includes a pulse generator connected to all the slip detection circuits and arranged to apply thereto a ramp input simulating an all-wheel skid condition, a further timer circuit arranged to produce an output for inhibiting the detection circuits and also for illuminating said warning lamp, and memory means sensitive to the outputs of the back e.m.f. detecting means to initiate resetting of the further timer circuit to de-inhibit the detector circuits and turn off said lamp after a delay follower receipt of simultaneous signals from said back e.m.f. detecting means.

8. A system as claimed in claim 7, in which the further timer circuit comprises a resistor-capacitor circuit including a diode connected to decrease the charging time constant of the circuit relative to the discharging time constant thereof, said circuit being connected to a power supply rail to provide a charging path and to said memory means which provides a discharge path and a trigger circuit with hysteresis controlled by the voltage on said capacitor.

9. An anti-skid braking system, comprising

a wheel sensor providing an output in response to wheel speed,

means operatively connected to said sensor output and providing a slippage output in response to sensed wheel slippage,

coil means operatively connected to said slippage means and selectively energized in response to said slippage output to provide a brake control output,

means operatively connected to said coil means and selectively providing a timing sequence in response to the energisation of said coil means and providing a warning output in response to a timing sequence of a predetermined duration,

detecting means operatively connected to said coil means and providing a back e.m.f. responsive output in response to the deactivation of said coil means, and

reset means operatively connected to said detecting means and resetting said timing sequence of said timing means in response to said back e.m.f. responsive output.