Data processor analyzer and display system

• US 4,107,459 A
• Filed: 05/16/1977
• Issued: 08/15/1978
• Est. Priority Date: 05/16/1977
• Status: Expired due to Term

• Current Assignee: Conic Corporation
• Original Assignee: Conic Corporation
• Inventors: Stamper, Jerry Lee
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Sachs, Michael C.
• Application Number:
  US05/797,188
• Time in Patent Office: 456 Days
• Field of Search: 178/68, 178/69.1, 340/146.1 AG, 340/146.1 AQ, 340/146.1 AV, 364/900 MS File
• US Class Current: 375/368
• CPC Class Codes: H04J 3/0605 Special codes used as synchronising signal
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A system for distinguishing a digital signal in a received serial bit stream signal, and for displaying data represented by the distinguished digital signal is disclosed. The system is contained in a single console. The bits represent data in an original digital signal having a predetermined bit rate, a predetermined number of bits per word, a predetermined number of words per frame, and a predetermined number of frames per subframe, with there being a predetermined synchronizing code word in each frame for defining the frame. The system includes a processing network for processing the received signal to reconstruct the bits, to recognize the code word from the recognized bits, and to define the frames in response to recognition of the code word to thereby distinguish a digital signal having the predetermined number of bits per word, the predetermined number of words per frame, and the predetermined number of frames per subframe. A keyboard device is coupled to the processing network for enabling an operator to indicate the predetermined bit rate, the predetermined number of bits per words, the predetermined number of words per frame, the predetermined number of frames per subframe, and the predetermined code word to the processing network for programming the processing network to distinguish the digital signal. A cathode ray tube is coupled to the processing network for providing an instant visual feedback from the processor to the operator during operation of the keyboard device, of the programming indications that are indicated to the processing network by operation of the keyboard device and for providing a visual display of data represented by the distinguished digital signal. A tape recorder is coupled to the processing network for recording the programming indications that are provided to the processing network by operation of the keyboard device.

Claims

1. A system contained in a single console for distinguishing a digital signal in a received serial bit stream signal, wherein said bits represent data in an original digital signal having a predetermined bit rate, a predetermined number of bits per word, and a predetermined number of words per frame, with there being a predetermined synchronizing code word in each frame for defining said frame, comprising

processing means for processing said received signal to reconstruct said bits, to recognize said code word from said reconstructed bits, and to define said frames in response to recognition of said synchronizing code word, to thereby distinguish a digital signal having said predetermined number of bits per word, and said predetermined number of words per frame,

keyboard means coupled to the processing means for enabling an operator to indicate said predetermined bit rate, said predetermined number of bits per word, said predetermined number of words per frame and said predetermined code word to the processing means for programming the processing means to distinguish said digital signal;

and

cathode ray tube means coupled to the processing means for providing an instant visual feedback from the processing means to said operator during operation of said keyboard, of said programming indications that are indicated to the processing means by operation of the keyboard means, and for providing a visual display of data represented by said distinguished digital signal.

2. A system according to claim 1, wherein the cathode ray tube means is coupled to the processing means for displaying said programming indications and said data in a multiple page format.

3. A system according to claim 1, further comprising

tape recording means coupled to the processing means for recording said programming indications that are provided to the processing means by operation of the keyboard means.

4. A system according to claim 3, wherein the processing means include a random access memory for storing said programming indications that are provided to the processing means by operation of the keyboard means, and

the tape recording means are coupled to the random access memory for recording said programming indications that are stored in the random access memory and/or for storing said recorded programming indications in the random access memory.

5. A system according to claim 1 wherein the means within the processing means for reconstructing said bits comprises

amplifier means responsive to said received serial bit stream for providing a first reference signal having a level representative of the positive peak voltage of said bit stream, a second reference signal having a level representative of the negative peak voltage of said bit stream, and a third reference signal having a level that is the average of the levels of said first and second reference signals;

first comparator means for comparing each of said three reference signals with said received serial bit stream and for providing separate binary indications in response to each of said comparisons as to the relative levels of said reference signals with respect to said bit stream;

second comparator means for comparing two sets of said binary indications provided at two consecutive bit times clocked by a first clock signal having said predetermined bit rate;

gain adjusting means responsive to said comparison by said second comparator means for adjusting the gain of said amplifier means to adjust the voltage difference between said first and second reference signals to correspond to the voltage difference between said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate; and

level adjusting means responsive to said comparison by said second comparator means for adjusting the levels of said first and second reference signals provided by said amplifier means to correspond to the levels of said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

whereby said bits in said received serial bit stream may be reconstructed from the binary indications provided from said comparison by the first comparison means of said third reference signal with said received serial bit stream.

6. A system according to claim 5, further including means for reconstructing a said received serial bit stream that is noise contaminated to be free of noise, said reconstructing means comprising

first integrator means for separately and continuously integrating each of said three binary indications provided by the first comparator means over said predetermined bit period, with said integration being continuously updated in response to a second clock signal having a clock rate that is a predetermined multiple of said predetermined bit rate, wherein three separate integrated signals are provided;

logic means for continuously examining said three integrated signals and for providing a weighted binary output signal having a sign corresponding to the majority sign of said three integrated signals; and

means for sampling said weighted binary output signal in response to said first clock signal at said predetermined bit rate for providing said noise free reconstructed serial bit stream.

7. A system according to claim 1, further including means for reconstructing a said received serial bit stream that is noise contaminated to be free of noise, said reconstructing means comprising

amplifier means responsive to said received serial bit stream for providing a first reference signal having a level representative of the positive peak voltage of said bit stream, a second reference signal having a level representative of the negative peak voltage of said bit stream, and a third reference signal having a level that is the average of the levels of said first and second reference signals;

first comparator means for comparing each of said three reference signals with said received serial bit stream and for providing separate binary indications in response to each of said comparisons as to the relative levels of said reference signals with respect to said bit stream;

second comparator means for comparing two sets of said binary indications provided at two consecutive bit times clocked by a first clock signal having said predetermined bit rate;

gain adjusting means responsive to said comparison by said second comparator means for adjusting the gain of said amplifier means to adjust the voltage difference between said first and second reference signals to correspond to the voltage difference between said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

level adjusting means responsive to said comparison by said second comparator means for adjusting the levels of said first and second reference signals provided by said amplifier means to correspond to the levels of said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

first integrator means for separately and continuously integrating each of said three binary indications provided by the first comparator means over said predetermined bit period, with said integration being continuously updated in response to a second clock signal having a clock rate that is a predetermined multiple of said predetermined bit rate, wherein three separate integrated signals are provided;

logic means for continuously examining said three integrated signals and for providing a weighted binary output signal having a sign corresponding to the majority sign of said three integrated signals; and

means for sampling said weighted binary output signal in response to said first clock signal at said predetermined bit rate for providing said noise free reconstructed serial bit stream.

8. A system according to claim 7, further including means for synchronizing said first clock signal with said reconstructed serial bit stream, said synchronizing means comprising

phase detector means for detecting any difference in phase between said reconstructed serial bit stream and said first clock signal and for providing a phase error signal in response to said detected difference;

and

first clock means for generating said first clock signal in response to said second clock signal and for shifting the phase of said first clock signal in response to said phase error signal to be in phase with said reconstructed serial bit stream.

9. A system according to claim 8, wherein the phase detector means include means for detecting said phase difference by examining the sign of said integrated signal provided by said integration of said binary indication produced in response to said comparison of said third reference signal with said received serial bit stream upon each occurrence of a bit transition in said reconstructed serial bit stream.

10. A system according to claim 8, further including limiting means for limiting the rate at which said first clock means shifts the phase of said first clock signal, said limiting means comprising

second integrator means for integrating said phase error signal over a predetermined duration to provide a limited phase error signal;

wherein the first clock means effects said phase shift in response to said limited phase error signal.

11. A system according to claim 10, further including locking means for locking the frequency of said first clock signal to the frequency of said reconstructed serial bit stream, said locking means comprising

third integrator means for integrating said limited phase error signal over a given duration to provide an integrated phase error signal,

means responsive to said integrated phase error signal for computing the bit rate of said reconstructed serial bit stream and for providing a bit rate indication signal for indicating said computed bit rate;

and

second clock means for generating said second clock signal in response to a reference frequency signal, wherein the second clock means responds to said bit rate indication signal to adjust the frequency of said second clock signal to be said predetermined multiple of said computed bit rate.

12. A system according to claim 8, further including locking means for locking the frequency of said first clock signal to the frequency of said reconstructed serial bit stream, said locking means comprising

second integrator means for integrating said phase error signal over a given duration to provide an integrated phase error signal,

means responsive to said integrated phase error signal for computing the bit rate of said reconstructed serial bit stream and for providing a bit rate indication signal for indicating said computed bit rate;

and

second clock means for generating said second clock signal in response to a reference frequency signal, wherein the second clock means responds to said bit rate indication signal to adjust the frequency of said second clock signal to be said predetermined multiple of said computed bit rate.

13. A system according to claim 1 wherein the means within the processing means for recognizing the predetermined synchronizing code word comprises,

means for storing said predetermined code word having a given number of bits,

means for registering said given number of consecutive bits in said reconstructed serial bit stream;

indicator means for comparing said stored code word with said registered bits and for providing an error indication of the number of bits positions where there is a disagreement between said code word and said registered bits;

comparator means for comparing said error indications and for storing any error indication that is lower than a previously provided error indication, wherein said comparator means provide a sync error pulse each time a said lower error indication is provided,

word counter means for counting words at the predetermined number of bits per word rate in response to a bit clock signal providing bits at the predetermined bit rate, wherein a count of words is initiated in response to said sync error pulse,

frame counter means for counting frames at the predetermined number of words per frame rate in response to a word count signal provided by the word counter means, wherein a frame pulse signal is provided upon counting each frame, with the comparator means responding to said frame sync pulse by clearing said lower indication from said storage,

logic means responsive to said frame pulse signal and to said bit clock signal for defining a one bit duration window at the beginning of each frame and for examining whether said sync error pulse occurs within said window;

wherein when said sync error pulse occurs within said window for a predetermined number of consecutive frames, said sync control logic means causes the counters to operate in a lock mode wherein said word count is not reinitiated in response to a sync error pulse accuring at some time other than in said window.

14. A system according to claim 13, wherein said sync control logic means causes the counters to cease operating in said lock mode when said sync error signal does not occur within said window for a predetermined number of consecutive frames.

15. A system for distinguishing a digital signal in a received serial bit stream signal, wherein said bits represent data in an original digital signal having a predetermined bit rate, characterized by

means for reconstructing said bits comprising

amplifier means responsive to said received serial bit stream for providing a first reference signal having a level representative of the positive peak voltage of said bit stream, a second reference signal having a level representative of the negative peak voltage of said bit stream, and a third reference signal having a level that is the average of the levels of said first and second reference signals;

first comparator means for comparing each of said three reference signals with said received serial bit stream and for providing separate binary indications in response to each of said comparisons as to the relative levels of said reference signals with respect to said bit stream;

second comparator means for comparing two sets of said binary indications provided at two consecutive bit times clocked by a first clock signal having said predetermined bit rate;

gain adjusting means responsive to said comparison by said second comparator means for adjusting the gain of said amplifier means to adjust the voltage difference between said first and second reference signals to correspond to the voltage difference between said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate; and

level adjusting means responsive to said comparison by said second comparator means for adjusting the levels of said first and second reference signals provided by said amplifier means to correspond to the levels of said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

whereby said bits in said received serial bit stream may be reconstructed from the binary indications provided from said comparison by the first comparison means of said third reference signal with said received serial bit stream.

16. A system for distinguishing a digital signal in a received serial bit stream signal, wherein said bits represent data in an original digital signal having a predetermined bit rate, characterized by

means for reconstructing a said received serial bit stream that is noise contaminated to be free of noise, said reconstructing means comprising

amplifier means responsive to said received serial bit stream for providing a first reference signal having a level representative of the positive peak voltage of said bit stream, a second reference signal having a level representative of the negative peak voltage of said bit stream, and a third reference signal having a level that is the average of the levels of said first and second reference signals;

first comparator means for comparing each of said three reference signals with said received serial bit stream and for providing separate binary indications in response to each of said comparisons as to the relative levels of said reference signals with respect to said bit stream;

second comparator means for comparing two sets of said binary indications provided at two consecutive bit times clocked by a first clock signal having said predetermined bit rate;

gain adjusting means responsive to said comparison by said second comparator means for adjusting the gain of said amplifier means to adjust the voltage difference between said first and second reference signals to correspond to the difference between said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

level adjusting means responsive to said comparison by said second comparator means for adjusting the levels of said first and second reference signals provided by said amplifier means to correspond to the levels of said positive and negative peaks in said received serial bit stream that occur at said predetermined bit rate;

first integrator means for separately and continuously integrating each of said three binary indications provided by the first comparator means over said predetermined bit period, with said integration being continuously updated in response to a second clock signal having a clock rate that is a predetermined multiple of said predetermined bit rate, wherein three separate integrated signals are provided;

logic means for continuously examining said three integrated signals and for providing a weighted binary output signal having a sign corresponding to the majority sign of said three integrated signals; and

means for sampling said weighted binary output signal in response to said first clock signal at said predetermined bit rate for providing said noise free reconstructed serial bit stream.

17. A system according to claim 16, further including means for synchronizing said first clock signal with said reconstructed serial bit stream, said synchronizing means comprising

phase detector means for detecting any difference in phase between said reconstructed serial bit stream and said first clock signal and for providing a phase error signal in response to said detected difference;

and

first clock means for generating said first clock signal in response to said second clock signal and for shifting the phase of said first clock signal in response to said phase error signal to be in phase with said reconstructed serial bit stream.

18. A system according to claim 17, wherein the phase detector means include means for detecting said phase difference by examining the sign of said integrated signal provided by said integration of said binary indication produced in response to said comparison of said third reference signal with said received serial bit stream upon each occurrence of a bit transition in said reconstructed serial bit stream.

19. A system according to claim 17, further including limiting means for limiting the rate at which said first clock means shifts the phase of said first clock signal, said limiting means comprising

second integrator means for integrating said phase error signal over a predetermined duration to provide a limited phase error signal;

wherein the first clock means effects said phase shift in response to said limited phase error signal.

20. A system according to claim 19, further including locking means for locking the frequency of said first clock signal to the frequency of said reconstructed serial bit stream, said locking means comprising;

third integrator means for integrating said limited phase error signal over a given duration to provide an integrated phase error signal,

means responsive to said integrated phase error signal for computing the bit rate of said reconstructed serial bit stream and for providing a bit rate indication signal for indicating said computed bit rate; and

second clock means for generating said second clock signal in response to a reference frequency signal, wherein the second clock means responds to said bit rate indication signal to adjust the frequency of said second clock signal to be said predetermined multiple of said computed bit rate.

21. A system according to claim 17, further including locking means for locking the frequency of said first clock signal to the frequency of said reconstructed serial bit stream, said locking means comprising

second integrator means for integrating said phase error signal over a given duration to provide an integrated phase error signal,

means responsive to said integrated phase error signal for computing the bit rate of said reconstructed serial bit stream and for providing a bit rate indication signal for indicating said computed bit rate;

and

second clock means for generating said second clock signal in response to a reference frequency signal, wherein the second clock means responds to said bit rate indication signal to adjust the frequency of said second clock signal to be said predetermined multiple of said computed bit rate.

22. A system for distinguishing a digital signal in a received serial bit stream signal, wherein said bits represent data in an original digital signal having a predetermined bit rate, a predetermined number of bits per word, and a predetermined number of words per frame, with there being a predetermined synchronizing code word in each frame for defining said frame, comprising

processing means for processing said received signal to reconstruct said bits, to recognize said code word from said reconstructed bits, and to define said frames in response to recognition of said synchronizing code word, to thereby distinguish a digital signal having said predetermined number of bits per word, and said predetermined number of words per frame;

wherein the means within the processing means for recognizing said predetermined synchronizing code word comprises

means for storing said predetermined code word having a given number of bits,

means for registering said given number of consecutive bits in said recognized serial bit stream;

indicator means for comparing said stored code word with said registered bits and for providing an error indication of the number of bit positions where there is disagreement between said code word and said registered bits;

comparator means for comparing said error indications and for storing any error indication that is lower than a previously provided error indication, wherein said comparator means provide a sync error pulse each time a said lower error indication is provided,

word counter means for counting words at the predetermined number of bits per word rate in response to a bit clock signal providing bits at the predetermined bit rate, wherein a count of words is initiated in response to said sync error pulse,

frame counter means for counting frames at the predetermined number of words per frame rate in response to a word count signal provided by the word counter means, wherein a frame pulse signal is provided upon counting each frame, with the comparator means responding to said frame sync pulse by clearing said lower indication from said storage,

logic means responsive to said frame pulse signal and to said bit clock signal for defining a one bit duration window at the beginning of each frame and for examining whether said sync error pulse occurs within said window;

wherein when said sync error pulse occurs within said window for a predetermined number of consecutive frames, said sync control logic means causes the counters to operate in a lock mode wherein said word count is not reinitiated in response to a sync error pulse occurring at some time other than in said window.

23. A system according to claim 22, wherein said sync control logic means causes the counters to cease operating in said lock mode when said sync error signal does not occur within said window for a predetermined number of consecutive frames.