Method and apparatus for addressing a digital memory

• US 4,107,717 A
• Filed: 11/17/1976
• Issued: 08/15/1978
• Est. Priority Date: 11/18/1975
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Klotzner, Winfried, Daumer, Rolf, DU Mont, Hans-Christoph, Busse, Wolfgang
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/742,921
• Time in Patent Office: 636 Days
• Field of Search: 235/150.21, 235/150.2, 235/151, 123/32 AE, 123/32 EA, 364/431, 364/200 MS File, 364/900 MS File
• US Class Current: 139/383.0AA
• CPC Class Codes: F02B 2075/027 four
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor

Abstract

A central digital memory contains data relating values of operational variables of an installation to values of a stored parameter. The central memory is addressed in parallel via input lines carrying the address of the stored data. The address is generated by selecting one of several discrete input lines leading to an address selector memory which contains preliminary addresses related to the various operational states of the installation. A portion of the preliminary address is delivered directly to the central memory whereas another portion is used to preset a counter. If the particular operational state is dependent on another parameter, for example temperature, a temperature-dependent clocking frequency is admitted to the counter and alters its contents which are then used to supplement the first portion of the address already delivered to the central memory. If no temperature dependency exists, the second portion of the address is passed on without change.

Claims

1. A method for addressing a central memory for interrogation thereof and retrieval of data stored therein, said addressing taking place in dependence on the operational states of a system which is itself controlled by the data in said central memory, at least one of said operational states being dependent on another state, preferably the temperature of the system, and in particular adapted to controlling an electronic fuel injection system for generating a correction frequency by using the data retrieved from said central memory, for processing by a main processor and for generation of injection pulses to control the opening times of fuel injection valves of the engine, the improvement comprising:

deriving switching signals from prevailing operational states of the system and feeding said switching signals to a decoder circuit, cyclically activating said decoder for generating a single pre-address selector signal corresponding to each combination of operational states, said pre-address selector signal being fed to an address memory for generating a digital address, a first part of which is fed directly to said main processor for selecting an address range and a second portion of which being fed to a counter which is thereby set to an initial value, gating said counter for a predetermined length of time, feeding to said counter a clock pulse train dependent on said operational state of the system, thereby causing said counter to count upwardly from its initial value, and delivering the final contents of said counter at the expiration of said gating time to said central memory for providing the complete address therein, and closing the gating input to said counter if a particular combination of operational states is independent of said other operational state.

2. In an apparatus for addressing a central memory for interrogation thereof and retrieval of data stored therein, said addressing taking place in dependence on the operational states of a system which is itself controlled by the data in said central memory, at least one of said operational states being dependent on another state, preferably the temperature of the system, and in particular adapted to controlling an electronic fuel injection system for generating a correction frequency by using the data retrieved from said central memory, for processing by a main processor and for generation of injection pulses to control the opening times of fuel injection valves of the engine, the improvement comprising:

means for sensing operational states of the controlled system, means for generating switching signals from said sensed states, decoder means for receiving said switching signals and for generating a plurality of single signals activated in cyclic manner for delivery to an address memory containing address data, the output of said address memory being divided into a first portion and a second portion, said first portion being fed to a central memory and said second portion being fed to a counter for initialization of the contents thereof, means for generating a temperature-dependent frequency and gating means for admitting said temperature-dependent frequency to said counter for continuous counting from said initialized count;

whereby, when the gating means have terminated the gating process, said counter contains a number for delivery to said central memory to form together with said first portion an address for delivery of a datum associated therewith in said central memory.

3. An apparatus as defined by claim 2, wherein said means for generating a temperature-dependent frequency is a temperature-dependent element located in the vicinity of the coolant of the engine and an oscillator connected to said element, sensitive to changes of resistance in said temperature-dependent element, thereby producing an output train whose frequency is temperature - proportional and wherein said second portion of said output from said address memory is the five least significant data bits which are delivered to said counter as an initializing content.

4. An apparatus as defined by claim 3, further comprising a synchronizing circuit for receiving said temperature-dependent frequency train, the output of said synchronizing circuit being connected to a gating circuit for gating said counter.

5. An apparatus as defined by claim 2, further comprising a main divider circuit and means for feeding to said main divider circuit a master clock frequency, said main divider circuit serving to generate a multitude of mutually synchronized sub-frequencies.

6. An apparatus as defined by claim 4, further comprising gate control circuitry for generating a variable gate control pulse fed to said gating circuit and for generating a further control pulse fed to said counter for causing the latter to accept the partial address constituted by said second portion from its respective input terminals.

7. An apparatus as defined by claim 2, further comprising range sensor means for altering the output from said counter in dependence on temperature, said range sensor means receiving at its input the output data from said counter, said range sensor means forming a binary word corresponding to the lowest temperature and being equal to a logical 0 on all of its outputs when, at the termination of said gating interval, said counter has not reached its maximum count, and for transferring without change the output of said counter when said counter has exceeded its maximum capacity once after the expiration of said gating time and for generating a binary output word corresponding to the maximum temperature of the installation when said counter has reached its maximum capacity twice after the expiration of said gating time.

8. An apparatus as defined by claim 7, wherein said range sensing means is so embodied that when the content of said counter has reached its maximum capacity twice at the expiration of said gating time, said range sensing means delivers to said gate circuit a signal causing said counter to remain at its maximum count.

9. An apparatus as defined by claim 2, wherein said address memory includes a plurality of storage locations each having 8-bits capacity, wherein when said decoder circuit selects a particular input line, said address memory delivers at its output an 8-bit word, the three most significant bits of which constitute the pre-address of said central memory which is delivered directly to said central memory whereas the remaining five least significant bits are fed to the pre-set inputs of said counter, said counter being a 5-bit counter which counts upwardly at a clock frequency provided by said temperature-dependent pulse train during a time defined by said gating circuit.

10. An apparatus as defined by claim 2, further comprising gate controller means for providing two distinct gating periods to said gating circuit;

whereby, during operational conditions substantially influenced by temperature, said counter receives a gating period utilizing its maximum capacity whereas during other operational conditions also dependent on temperature said counter receives a gating period limiting it to one-half of its total capacity.

11. An apparatus as defined by claim 2, wherein said sensor means for sensing operational conditions of the engine include switch means and exhaust gas sensor means for generating said signals fed to said decoder, and further comprising synchronizing means connected ahead of said decoder for placing said signals in a mutually fixed synchronized time frame.

12. An apparatus as defined by claim 11, wherein said synchronizing means includes bistable flip-flops for receiving said signals from said switches and sensors and being clocked by one of said sub-frequencies whereby the outputs of said bistable flip-flops generate mutually synchronized signals relating to the operational conditions of the installation.

13. An apparatus as defined by claim 2, further comprising a 3-bit counter serving as an idling counter receiving a counting pulse train of low frequency connected to a flip-flop which is set by the output of said idling counter when an appropriate idling gate signal releases said idling counter for counting.

14. An apparatus as defined by claim 13, wherein the output from said flip-flop controlled by said idling counter is fed to said decoder circuit if simultaneously an idling signal has become extinct due to an increase of engine speed wherein said flip-flop is resettable to its normal state by an operational signal related to start-up fuel enrichment.

15. An apparatus as defined by claim 2, wherein said decoder circuit receives a plurality of coupled clock frequencies, thereby generating a cyclic activation scheme and wherein specific clock times related to said cyclic activation are delivered to logical coupling circuits which also receive said switching signals.

16. An apparatus as defined by claim 2, further comprising gate control circuitry for controlling said gating circuit, said gate control circuit including bistable flip-flops clocked by a master frequency, and further comprising a NOR gate feeding a first one of said flip-flops, said NOR gate receiving at one of its inputs a first sub-frequency and receiving at its second input another pulse frequency and wherein the output of said first flip-flop is connected to the input of said second flip-flop the output of which generates a signal defining the gating time of said counter.

17. An apparatus as defined by claim 16, wherein said gate control circuit includes a second NOR gate the output of which is connected to said first NOR gate and the input of which receives a signal defining an operational state requiring high precision and the other input of which receiving from an inverter a sub-frequency correlated with the sub-frequency fed to said first NOR gate.

18. An apparatus as defined by claim 17, wherein said gate control circuit includes third and fourth NOR gates receiving alternatively the outputs from said first and second flip-flops for generating a signal for conditioning said counter to receive an initialized content from said address memory and for generating a request signal indicating when the outputs of said addressing apparatus carries said address.

19. An apparatus as defined by claim 18, further comprising range sensor means for determining the number of times said counter has reached its maximum content during said gating period, said range sensing means including a first NOR gate for receiving in parallel the output from said counter, a flip-flop connected behind said first NOR gate and resettable by said pulse from said gate control circuit, the output of said flip-flop defining the operational state of means for altering the address from said counter.

20. An apparatus as defined by claim 19, wherein said range sensing circuit includes a second NOR gate which receives the output signals from said counter after passage through inverters and also receives the inverted output signal of said flip-flop connected behind said first NOR gate;

whereby, when the counter content reaches the maximum capacity a second time, a signal is generated which causes said gate circuit to interrupt delivery of the pulse train fed to said counter.

21. An apparatus as defined by claim 20, including another NOR gate receiving at one of its inputs a signal related to an operational state of the installation, the output of which is connected to one of the inputs of said second NOR gate for determining the upper limit of said counter.

22. An apparatus as defined by claim 2, further comprising pulse generator circuit means for receiving input signals related to operational states of the engine all of which are temperature-dependent and for generating an output signal when one of said input signals is selected during the cyclic operation of said decoder circuit for the purpose of calculating an address related to one of said operational states.

23. An apparatus as defined by claim 22, wherein the output signal from said pulse generator circuit and the output signal of said range sensing circuit are fed to a NOR gate within an address change circuit, the output of which so controls subsequent NOR gates that the output of said counter is changed when it has not reached its maximum count at the expiration of said gating period and wherein said address change circuit includes logical circuitry which uses the signal from said pulse generator circuit to prevent an address change for operational states of the installation which are not temperature-dependent, wherein the other inputs of said subsequent NOR gates receive the output signals from said counter after passage through inverters.

24. An apparatus as defined by claim 2, further comprising a synchronizer circuit for receiving transduced signals related to the conditions of said installation, and for rendering said signals mutually synchronized, said synchronizing circuit including first and second flip-flops connected in series, the clock input of said first flip-flop receiving said pulse train related to temperature and the output of said second flip-flop being connected to an input of a subsequent NOR gate the other input of which receives a signal from range sensing means indicating that the upper limit of said counter has been reached a second time, the output of said NOR gate being connected to one of the inputs of a subsequent NAND gate the other inputs of which receive a signal defining the gating time of said counter and a signal from a pulse generating circuit including the temperature-dependence of cyclically selected operational states of the installation.

25. An apparatus as defined by claim 24, wherein said gating circuit includes an AND gate connected to the counting input of a first partial counter of 4-bits and a second partial counter, said first and second partial counters constituting said counter.