Portable circuit tester

• US 4,108,358 A
• Filed: 03/22/1977
• Issued: 08/22/1978
• Est. Priority Date: 03/22/1977
• Status: Expired due to Term

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Rothenberg, Peter, Niemaszyk, Casimer
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/779,978
• Time in Patent Office: 518 Days
• Field of Search: 235/153 AC, 235/153 AK, 235/302, 324/73 R, 324/73 AT
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31914 Portable Testers

Abstract

A portable circuit tester is disclosed which features efficient and simplified testing and fault identification of electronic units, such as circuit cards or the like. The tester incorporates an executive test program stored in a programmable read-only Memory (PROM) and accepts programmable test information related to individual units under test from PROM cards. The combination of the executive test program and a PROM card automatically applies test patterns to the unit under test and which patterns perform a go/no go acceptance test or a fault isolation test as may be desired.

Claims

1. A system for testing electrical units, comprising:

programmable memory means for storing a test program relating to a particular unit to be tested;

executive memory means for storing an executive test program;

a central processing unit connected to the programmable memory means for reading the test program stored therein, and connected to the executive memory means for executing the executive test program in accordance with the read test program;

means connected to the central processing unit, the executive memory means and the unit to be tested, and controlled by the central processing unit for applying the executed executive test program to the unit to be tested; and

indicating means connected to the programmable memory means, the executive memory means, the central processing unit and the means for applying the executed executive test program to the unit to be tested, and operable by all of said means for indicating test operating instructions and unit test status.

2. A system as described by claim 1, wherein the programmable memory means for storing a test program relating to a particular unit to be tested includes:

an erasable programmable read only memory device storing test progam variable data in a predetermined test format.

3. A system as described by claim 2, wherein the executive memory means for storing an executive test program includes:

an erasable programmable read only memory device storing program routines for the execution of a test program utilizing the test program variable data in a predetermined test format stored in the programmable memory means.

4. A system as described by claim 3, including:

a random access memory device connected to the erasable programmable read only memory device for providing a scratch pad memory during execution of the test program.

5. A system as described by claim 1, wherein the means connected to the central processing unit, the executive memory means and the unit to be tested, and controlled by the control processing unit for applying the executed executive test program to the unit to be tested includes:

a dual storage register arrangement including a data storage register and a data buffer register;

a tri-state TTL compatible receiver-driver arrangement including a driver logic amplifier and a receiver logic amplifier;

the central processing unit providing a first signal for enabling the data storage register to load and store executed executive test program data; and

the central processing unit providing a second signal for enabling the data buffer register to receive the executed program data transferred from the data storage register and therefrom through the logic driver amplifier to the unit to be tested.

6. A system as described by claim 5, including:

means controlled by the central processing unit for controlling the driver amplifier so that said amplifier is in one appropriate mode of send, receive and input/output modes.

7. A system as described by claim 5, wherein:

the receiver amplifier is connected to the driver amplifier, with the executed program data received by the data buffer register and transferred therefrom through the driver amplifier to the unit to be tested being received by the receiver amplifier; and

the central processing unit separately connected to the receiver amplifier for reading the data received thereby.